Split-layer design for double patterning lithography

• US 8,347,240 B2
• Filed: 10/29/2010
• Issued: 01/01/2013
• Est. Priority Date: 10/29/2010
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Agarwal, Kanak B., Liebmann, Lars W., Nassif, Sani R.
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US12/915,923
• Publication Number:
  US 20120110521A1
• Time in Patent Office: 795 Days
• Field of Search: 716/52, 716/53, 716/54, 716/55, 716/103, 716/106, 716/111, 716/136, 700/119, 700/120, 700/121, 430/5, 378/35
• US Class Current: 716/54
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

A mechanism is provided for converting a set of single-layer design rules into a set of split-layer design rules for double patterning lithography (DPL). The set of single-layer design rules and minimum lithographic resolution pitch constraints for single exposure are identified. The set of single-layer design rules comprise a first plurality of minimum distances that are required by a set of first shapes in a single-layer design. Each of the first plurality of minimum distances in the set of single-layer design rules are modified with regard to the minimum lithographic resolution pitch constraints for single exposure, thereby forming the set of split-layer design rules. The set of split-layer design rules comprise a second plurality of minimum distances that are required by a set of second shapes and a set of third shapes in a split-layer design. The set of split-layer design rules are then coded into a design rule checker.

Claims

1. A method, in a data processing system, for converting a set of single-layer design rules into a set of split-layer design rules for double patterning lithography (DPL), the method comprising:

identifying, by a processor in the data processing system, the set of single-layer design rules and minimum lithographic resolution pitch constraints for single exposure, wherein the set of single-layer design rules comprise a first plurality of minimum distances that are required by a set of first shapes in a single-layer design;

modifying, by the processor, each of the first plurality of minimum distances in the set of single-layer design rules with regard to the minimum lithographic resolution pitch constraints for single exposure, thereby forming the set of split-layer design rules, wherein the set of split-layer design rules comprise at least a second plurality of minimum distances that are required by at least a set of second shapes and a set of third shapes in a split-layer design; and

coding, by the processor, the set of split-layer design rules into a design rule checker for use in designing a double patterning lithography design.

2. The method of claim 1, wherein the set of split-layer design rules comprise a set of intra-layer rules for each exposure layer in the set of split-layer design rules and a set of inter-layer rules for elements between each exposure layer in the set of split-layer design rules.

3. The method of claim 1, further comprising:

generating, by the processor, a set of minimum overlap rules using a set of technology specific overlay specifications.

4. The method of claim 1, wherein generating the set of split-layer design rules includes multiplying a subset of the first plurality of minimum distances by a multiplier while another subset of the first plurality of minimum distances are reused, wherein the multiplier is determined based on the minimum lithographic resolution pitch constraints for the single exposure.

5. The method of claim 1, further comprising:

identifying, by the processor, a two-layer design to be validated using the set of split-layer design rules;

verifying, by the processor, for each shape in a plurality of shapes in the two-layer design, that each of the set of split-layer design rules required for the design have not been violated; and

responsive to the two-layer design failing to violate any of the set of split-layer design rules, generating, by the processor, a validated two-layer design.

6. The method of claim 5, further comprising:

responsive to two-layer design violating at least one of the set of split-layer design rules, identifying, by the processor, at least one of the set of split-layer design rules that is violated; and

indicating, by the processor, within the two-layer design, a location of where the at least one of the set of split-layer design rules is violated.

7. The method of claim 5, wherein verifying that each of the set of split-layer design rules required for the design-have not been violated comprises:

examining, by the processor, each polygon in the two-layer design;

measuring, by the processor, at least one layout parameter in the two-layer design for a set for layout features thereby forming a set of measurements; and

comparing, by the processor, the set of measurements to the set of split-layer design rules in order to identify violations of the set of split-layer design rules.

8. A computer program product comprising a non-transitory computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed on a computing device, causes the computing device to:

identify a set of single-layer design rules and minimum lithographic resolution pitch constraints for single exposure, wherein the set of single-layer design rules comprise a first plurality of minimum distances that are required by a set of first shapes in a single-layer design;

modify each of the first plurality of minimum distances in the set of single-layer design rules with regard to the minimum lithographic resolution pitch constraints for single exposure, thereby forming a set of split-layer design rules, wherein the set of split-layer design rules comprise at least a second plurality of minimum distances that are required by at least a set of second shapes and a set of third shapes in a split-layer design; and

code the set of split-layer design rules into a design rule checker for use in designing a double patterning lithography design.

9. The computer program product of claim 8, wherein the set of split-layer design rules comprise a set of intra-layer rules for each exposure layer in the set of split-layer design rules and a set of inter-layer rules for elements between each exposure layer in the set of split-layer design rules.

10. The computer program product of claim 8, wherein the computer readable program further causes the computing device to:

generate a set of minimum overlap rules using a set of technology specific overlay specifications.

11. The computer program product of claim 8, wherein the computer readable program to generate the set of split-layer design rules further causes the computing device to multiply a subset of the first plurality of minimum distances by a multiplier while another subset of the first plurality of minimum distances are reused, wherein the multiplier is determined based on the minimum lithographic resolution pitch constraints for the single exposure.

12. The computer program product of claim 11, wherein the computer readable program further causes the computing device to:

identify a two-layer design to be validated using the set of split-layer design rules;

verify, for each shape in a plurality of shapes in the two-layer design, that each of the set of split-layer design rules required for the design have not been violated; and

responsive to the two-layer design failing to violate any of the set of split-layer design rules, generate a validated two-layer design.

13. The computer program product of claim 11, wherein the computer readable program further causes the computing device to:

responsive to the two-layer design violating at least one of the set of split-layer design rules, identify at least one of the set of split-layer design rules that is violated; and

indicate, within the two-layer design, a location of where the at least one of the set of split-layer design rules is violated.

14. The computer program product of claim 11, wherein the computer readable program to verify that each of the set of split-layer design rules required for the design have not been violated further causes the computing device to:

examine each polygon in the two-layer design;

measure at least one layout parameter in the two-layer design for a set for layout features thereby forming a set of measurements; and

compare the set of measurements to the set of split-layer design rules in order to identify violations of the set of split-layer design rules.

15. An apparatus, comprising:

a processor; and

a memory coupled to the processor, wherein the memory comprises instructions which, when executed by the processor, cause the processor to;

identify a set of single-layer design rules and minimum lithographic resolution pitch constraints for single exposure, wherein the set of single-layer design rules comprise a first plurality of minimum distances that are required by a set of first shapes in a single-layer design;

modify each of the first plurality of minimum distances in the set of single-layer design rules with regard to the minimum lithographic resolution pitch constraints for single exposure, thereby forming a set of split-layer design rules, wherein the set of split-layer design rules comprise at least a second plurality of minimum distances that are required by at least a set of second shapes and a set of third shapes in a split-layer design; and

code the set of split-layer design rules into a design rule checker for use in designing a double patterning lithography design.

16. The apparatus of claim 15, wherein the set of split-layer design rules comprise a set of intra-layer rules for each exposure layer in the set of split-layer design rules and a set of interlayer rules for elements between each exposure layer in the set of split-layer design rules.

17. The apparatus of claim 15, wherein the instructions further cause the processor to:

generate a set of minimum overlap rules using a set of technology specific overlay specifications.

18. The apparatus of claim 15, wherein the instructions to generate the set of split layer design rules further cause the processor to multiply a subset of the first plurality of minimum distances by a multiplier while another subset of the first plurality of minimum distances are reused, wherein the multiplier is determined based on the minimum lithographic resolution pitch constraints for the single exposure.

19. The apparatus of claim 18, wherein the instructions further cause the processor to:

identify a two-layer design to be validated using the set of split-layer design rules;

verify, for each shape in a plurality of shapes in the two-layer design, that each of the set of split-layer design rules required for the design have not been violated; and

responsive to the two-layer design failing to violate any of the set of split-layer design rules, generate a validated two-layer design.

20. The apparatus of claim 18, wherein the instructions further cause the processor to:

responsive to the two-layer design violating at least one of the set of split-layer design rules, identify at least one of the set of split-layer design rules that is violated; and

indicate, within the two-layer design, a location of where the at least one of the set of split-layer design rules is violated.

21. The apparatus of claim 18, wherein the instructions to verify that each of the set of split-layer design rules required for the design have not been violated further cause the processor to:

examine each polygon in the two-layer design;

measure at least one layout parameter in the two-layer design for a set for layout features thereby forming a set of measurements; and

compare the set of measurements to the set of split-layer design rules in order to identify violations of the set of split-layer design rules.