Capacitive interface circuit for low power sensor system

• US 8,352,030 B2
• Filed: 07/13/2011
• Issued: 01/08/2013
• Est. Priority Date: 09/28/2006
• Status: Active Grant

• Current Assignee: Medtronic Incorporated (Medtronic Plc)
• Original Assignee: Medtronic Incorporated (Medtronic Plc)
• Inventors: Denison, Timothy J.
• Primary Examiner(s): Layno, Carl H
• Assistant Examiner(s): Stice, Paula J
• Application Number:
  US13/182,276
• Publication Number:
  US 20110267212A1
• Time in Patent Office: 545 Days
• Field of Search: 324/76, 324/38, 327/95
• US Class Current: 607/17
• CPC Class Codes: G01D 5/24 by varying capacitance

Abstract

A capacitive interface circuit for a low power system is described. The capacitive interface circuit is configured to achieve very low noise sensing of capacitance-based transducers, such as a micro-electro-mechanical system (MEMS)-based sensor, with high resolution and low power. The capacitive interface circuit uses a differential amplifier and correlated triple sampling (CTS) to substantially eliminate, or at least reduce, kT/C noise, as well as amplifier offset and flicker (1/f) noise, from the output of the amplifier. The capacitive interface circuit may further include an output stage that reduces glitching, i.e., clock transients, in the output signal by allowing transients in the amplifier output to settle. In this manner, the circuit can be used in a low power system to produce a stable, low-noise output.

Claims

1. An implantable medical device, comprising:

a correlated sampling circuit that reduces one or more noise components in an output signal, the correlated sampling circuit comprising;

a differential amplifier that amplifies a sensor signal to produce the output signal, wherein the differential amplifier comprises a first input, a second input, and an output; and

a sampling capacitor comprising an input coupled to the output of the differential amplifier, wherein the sampling capacitor stores the output signal; and

a clock distribution network that controls the correlated sampling circuit,

wherein the correlated sampling circuit controls the first and second inputs of the differential amplifier, responsive to timing signals provided by the clock distribution network, such that the differential amplifier amplifies the one or more noise components during at least a portion of a first clock phase and amplifies the sensor signal with the one or more noise components during a second clock phase, to reduce the one or more noise components in the output signal.

2. The device of claim 1, wherein the first input of the differential amplifier is coupled to a first capacitive sensor element, and wherein the second input of the differential amplifier is coupled to a second capacitive sensor element.

3. The device of claim 1, wherein the correlated sampling circuit couples an output of the sampling capacitor to ground during the first clock phase, couples the first and second inputs to ground during a first portion of the first clock phase, decouples the first and second inputs from ground during a second portion of the first clock phase, decouples the output of the sampling capacitor from ground during the second clock phase, couples the first and second capacitive sensor elements to a reference voltage during the second clock phase, and decouples the first and second capacitive sensor elements from the reference voltage during the first clock phase.

4. The device of claim 3, wherein the sampling capacitor receives the one or more amplified noise components during both the first clock phase and the second clock phase, and substantially reduces or eliminates at least the portion of the one of more amplified noise components during the second clock phase to reduce the one or more amplified noise components in the output signal.

5. The device of claim 1, wherein:

the first input of the differential amplifier is coupled to a first capacitive sensor element and the second input of the differential amplifier is coupled to a second capacitive sensor element; and

wherein the correlated sampling circuit further comprises;

a first switch that couples an output of the sampling capacitor to ground during the first clock phase and decouples the output of the sampling capacitor from ground during the second clock phase;

a second switch that couples the first input of the differential amplifier to ground during a first portion of the first clock phase and decouples the first input of the differential amplifier from ground during a second portion of the first clock phase;

a third switch that couples the second input of the differential amplifier to ground during the first portion of the first clock phase and decouples the second input of the differential amplifier from ground during a second portion of the first clock phase; and

a fourth switch that couples a reference voltage to the first and second capacitive sensor elements during the second clock phase and decouples the reference voltage from the first and second capacitive sensor elements during the first clock phase.

6. The device of claim 1, wherein the sampling capacitor stores the one or more amplified noise components from the differential amplifier in at least the portion of the first clock phase, receives the amplified sensor signal with the one or more amplified noise components from the differential amplifier during the second clock phase, and blocks the one or more amplified noise components to reduce the one or more amplified noise components in the output signal.

7. The device of claim 1, wherein the differential amplifier receives the sensor signal from first and second capacitive sensor elements, and wherein each of the first and second capacitive sensor elements has a first capacitor plate coupled to an input of the differential amplifier and a second capacitor plate coupled to a reference voltage.

8. The device of claim 1, wherein the differential amplifier receives the sensor signal from first and second capacitive sensor elements, and wherein each of the first and second capacitive sensor elements has a first capacitor plate coupled to an input of the differential amplifier and a second capacitor plate coupled to ground.

9. The device of claim 1, further comprising:

a ping-pong demodulator that samples and holds an output of the correlated sampling circuit in first and second output stages on an alternating basis.

10. The device of claim 9, wherein each of the output stages holds the output of the correlated sampling circuit for an amount of time sufficient to permit settling of at least some undesirable transients.

11. The device of claim 9, wherein the first output stage comprises an amplifier and a hold capacitor.

12. The device of claim 11, wherein the amplifier and the holdback capacitor form an integrator.

13. The device of claim 9, further comprising a feedback path between an output of the ping-pong demodulator and an input to the ping-pong demodulator.

14. The device of claim 9, wherein the feedback path comprises:

at least one feedback capacitor that provides negative feedback to the output of the correlated sampling circuit.

15. The device of claim 14, wherein the feedback path further comprises:

at least one switch configured to control a voltage stored on the feedback capacitor.

16. The device of claim 15, wherein the at least one switch is configured to alternate between coupling the feedback capacitor to a reference voltage and an output of the ping-pong demodulator.

17. The device of claim 16, wherein the at least one switch comprises a first switch and a second switch, and wherein the first switch is configured to couple the feedback capacitor to the reference voltage during at least a portion of the first clock phase, and couple the feedback capacitor to the output of the ping-pong demodulator during at least a portion of the second clock phase.

18. The device of claim 9, further comprising:

a first differential feedback path coupled between the output of the ping-pong demodulator and the first input of the differential amplifier, and a second differential feedback path coupled between the output of the ping-pong demodulator and the second input the differential amplifier.

19. The device of claim 18, wherein the first input of the differential amplifier is coupled to a first capacitive sensor element of a pressure sensor, and wherein the second input of the differential amplifier is coupled to a second capacitive sensor element of a pressure sensor.

20. The device of claim 19, wherein the first feedback path comprises a first feedback capacitor, and wherein the second feedback path comprises a second feedback capacitor.

21. The device of claim 20, wherein the first feedback capacitor comprises a first end coupled to the first input of the differential amplifier, and wherein the second feedback capacitor comprises a second end coupled to the second input of the differential amplifier.

22. The device of claim 21, wherein the first feedback capacitor comprises a second end coupled to a first at least one switch, and wherein the second feedback capacitor comprises a second end coupled to a second at least one switch.

23. The device of claim 22, wherein the first at least one switch comprises a first switch configured to couple the first feedback capacitor to the output of the ping-pong demodulator, and a second switch configured to couple the first feedback capacitor to ground or a reference voltage.

24. The device of claim 23, wherein the second at least one switch comprises a first switch configured to couple the second feedback capacitor to the output of the ping-pong demodulator, and a second switch configured to couple the second feedback capacitor to ground or a reference voltage.

25. A method for operating an implantable medical device, comprising:

amplifying, via a differential amplifier, a differential sensor signal to produce an output signal, wherein the differential amplifier comprises a first input, a second input, and an output;

storing the output signal on a sampling capacitor comprising an input coupled to the output of the differential amplifier; and

applying a correlated sampling process to reduce one or more noise components in the output signal, wherein applying the correlated sampling process includes controlling the first and second inputs of the differential amplifier, responsive to timing signals provided by a clock distribution network, such that the differential amplifier amplifies the one or more noise components during at least a portion of a first clock phase and amplifies the differential sensor signal with the one or more noise components during a second clock phase, to reduce the one or more noise components in the output signal.

26. The method of claim 25, wherein the first input of the differential amplifier is coupled to a first capacitive sensor element, and wherein the second input of the differential amplifier is coupled to a second capacitive sensor element.

27. The method of claim 25, wherein the correlated sampling process comprises coupling an output of the sampling capacitor during the first clock phase, coupling the first and second inputs to ground during a first portion of the first clock phase, decoupling the first and second inputs from ground during a second portion of the first clock phase, decoupling the output of the sampling capacitor from ground during the second clock phase, coupling the first and second capacitive sensor elements to a reference voltage during the second clock phase, and decoupling the first and second capacitive sensor elements from the reference voltage during the first clock phase.

28. The method of claim 27, further comprising receiving the one or more amplified noise components at the sampling capacitor during both the second portion of the first clock phase and the second clock phase, and substantially reducing or eliminating at least the portion of the one of more amplified noise components via the sampling capacitor during the second clock phase to reduce the one or more amplified noise components in the output signal.

29. The method of claim 27, wherein;

the first input of the differential amplifier is coupled to a first capacitive sensor element and the second input of the differential amplifier is coupled to a second capacitive sensor element; and

wherein the correlated sampling process comprises;

coupling an output of the sampling capacitor to ground during the first clock phase and decoupling the output of the sampling capacitor from ground during the second clock phase;

coupling the first input of the differential amplifier to ground during the first portion of a first clock phase and decoupling the first input of the differential amplifier from ground during a second portion of the first clock phase;

coupling the second input of the differential amplifier to ground during the first portion of the first clock phase and decoupling the second input of the differential amplifier from ground during a second portion of the first clock phase; and

coupling a reference voltage to the first and second capacitive sensor elements during the second clock phase and decoupling the reference voltage from the first and second capacitive sensor elements during the first clock phase.

30. The method of claim 29, further comprising storing the one or more amplified noise components from the differential amplifier in the sampling capacitor in at least the portion of the first clock phase, receiving the amplified differential sensor signal with the one or more amplified noise components from the differential amplifier in the sampling capacitor during the second clock phase, and blocking the one or more amplified noise components via the sampling capacitor to reduce the one or more amplified noise components in the output signal.

31. The method of claim 27, further comprising sampling and holding an output of the sampling capacitor in first and second output stages of a ping-pong demodulator on an alternating basis, wherein each of the output stages holds the output of the sampling capacitor for an amount of time sufficient to permit settling of at least some undesirable transients.

32. The method of claim 31, further comprising applying a feedback signal via a feedback path from an output of the ping-pong demodulator to an input to the ping-pong demodulator.

33. The method of claim 32, wherein the feedback path comprises:

at least one feedback capacitor that provides negative feedback to the output of the correlated sampling circuit.

34. The method of claim 33, further comprising:

controlling, using at least one switch, a voltage stored on the feedback capacitor.

35. The method of claim 33, alternating, using the at least one switch, between coupling the feedback capacitor to a reference voltage and an output of the ping-pong demodulator.

36. The method of claim 31, further comprising applying feedback signals via a first differential feedback path coupled between an output of the ping-pong demodulator and the first input of the differential amplifier, and a second differential feedback path coupled between an output of the ping-pong demodulator and the second input of the differential amplifier.

37. The method of claim 36, wherein the first input of the differential amplifier is coupled to a first capacitive sensor element of a pressure sensor, and wherein the second input of the differential amplifier is coupled to a second capacitive sensor element of a pressure sensor.

38. The method of claim 36, wherein the first feedback path comprises a first feedback capacitor, and wherein the second feedback path comprises a second feedback capacitor.

39. The method of claim 38, wherein the first feedback capacitor comprises a first end coupled to the first input of the differential amplifier, and wherein the second feedback capacitor comprises a second end coupled to the second input of the differential amplifier.

40. The method of claim 38, wherein the first feedback capacitor comprises a second end coupled to a first at least one switch, and wherein the second feedback capacitor comprises a second end coupled to a second at least one switch.

41. The method of claim 40, wherein the first at least one switch comprises a first switch and a second switch, and further comprising:

coupling, using the first switch, the first feedback capacitor to the output of the ping-pong demodulator; and

coupling, using the second switch, the first feedback capacitor to ground or a reference voltage.

42. The method of claim 40, wherein the second at least one switch comprises a first switch and a second switch, and further comprising:

coupling, using the first switch, the second feedback capacitor to the output of the ping-pong demodulator; and

coupling, using the second switch, the second feedback capacitor to ground or a reference voltage.

43. An implantable medical device, comprising:

means for amplifying a differential sensor signal to produce an output signal, wherein the means for amplifying comprises a first input, a second input, and an output;

means for storing the output signal on a sampling capacitor coupled to the output of the means for amplifying; and

means for applying a correlated sampling process that reduces one or more noise components in the output signal, wherein the means for applying the correlated sampling process comprises means for controlling the first and second inputs of the means for amplifying, responsive to timing signals provided by a clock distribution network that controls the means for applying, such that the means for amplifying amplifies the one or more noise components during at least a portion of a first clock phase and amplifies the differential sensor signal with the one or more noise components during a second clock phase, to reduce the one or more noise components in the output signal.