Programmable microcontroller architecture(mixed analog/digital)

• US 8,358,150 B1
• Filed: 10/11/2010
• Issued: 01/22/2013
• Est. Priority Date: 10/26/2000
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Snyder, Warren, Mar, Monte
• Primary Examiner(s): TRAN, ANH Q
• Application Number:
  US12/902,137
• Time in Patent Office: 834 Days
• Field of Search: None
• US Class Current: 326/41
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06G 7/06 Programming arrangements, e.g. plugboard for interconnecting functional units of the computer; Digital programming hybrid computers G06J
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03K 19/08 using semiconductor devices H03K19/173 takes precedence; wherein the semiconductor devices are only diode rectifiers H03K19/12
• CPC Class Codes: H03K 19/173 using elementary logic circuits as components
• CPC Class Codes: H03K 19/1733 Controllable logic circuits H03K19/177 takes precedence
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/014 Modifications of generator to ensure starting of oscillations
• CPC Class Codes: H03K 3/02315 Stabilisation of output, e.g. using crystal

Abstract

A circuit formed in an integrated circuit (chip) is disclosed. The circuit can include a plurality of analog circuit blocks each configured to provide at least one analog function; at least one digital circuit block that provides a digital function; and a programmable interconnect coupled to the analog circuit blocks and configurable to interconnect combinations of the analog circuit blocks to one another. The programmable interconnect can include a plurality of multiplexer (MUX) circuits including port MUX circuits coupled between the analog circuit blocks and ports that provide signal connections for the chip.

Claims

1. A circuit, comprising:

a plurality of analog circuit blocks, each configured to provide at least one analog function;

at least one digital circuit block that provides a digital function; and

a programmable interconnect coupled to the analog circuit blocks and configurable to interconnect combinations of the analog circuit blocks to one another, wherein the circuit is formed in an integrated circuit (chip), and wherein the programmable interconnect comprises a plurality of multiplexer (MUX) circuits including port MUX circuits coupled between the analog circuit blocks and ports that provide signal connections for the chip.

2. The circuit of claim 1, wherein:

the at least one digital block includes a plurality of digital blocks that each provides at least one digital function; and

the programmable interconnect is further coupled to the digital circuit blocks and configurable to interconnect combinations of the digital circuit blocks to one another.

3. The circuit of claim 1, wherein:

the plurality of multiplexer (MUX) circuits have MUX inputs and MUX outputs coupled to the analog circuit blocks.

4. The circuit of claim 3, wherein:

the circuit is formed in an integrated circuit (chip); and

the MUX circuits include block MUX circuits coupled to the analog circuits.

5. The circuit of claim 1, wherein:

the programmable interconnect is programmable to provide multiple signal paths between same analog circuit blocks.

6. The circuit of claim 1, wherein:

the analog circuit blocks are selected from the group of;

analog continuous time amplifiers and switched capacitor type circuits.

7. A circuit, comprising:

a programmable interconnect configurable to enable multiple signal routing between signal paths;

a plurality of analog circuit blocks formed in a same integrated circuit (chip) having inputs and outputs coupled to the signal paths, each analog block providing at least one analog function, wherein the programmable interconnect comprises a plurality of multiplexer (MUX) circuits including port MUX circuits coupled between the analog circuit blocks and ports that provide signal connections for the chip; and

at least one digital circuit block formed in the chip that provides at least one digital function.

8. The circuit of claim 7, wherein:

the programmable interconnect is configurable to connect multiple analog blocks in series with one another.

9. The circuit of claim 7, wherein:

the at least one digital circuit block includes a plurality of digital circuit blocks formed in the chip having inputs and outputs coupled to the signal paths.

10. The circuit of claim 7, further including:

an internal input/output (110) bus having bus lines coupled to the signal paths.

11. The circuit of claim 7, wherein:

each analog circuit block is programmable between at least one of a plurality of different analog functions.

12. The circuit of claim 7, wherein:

the chip includes at least one port as a signal connection point;

the programmable interconnect is configurable to connect the at least one port to any of the analog circuit blocks.

13. The circuit of claim 12, wherein:

the programmable interconnect is configurable to provide an analog signal input path from the at least one port to any of the analog circuit blocks.

14. The circuit of claim 12, wherein:

the programmable interconnect is configurable to provide an analog signal output path from any of the analog circuit blocks to the at least one port.

15. A method, comprising:

providing at least one digital circuit block in an integrated circuit (chip);

providing a plurality of analog circuit blocks in the chip; and

providing a programmable interconnect configurable to at least enable combinations of analog circuit blocks to be interconnected to combine analog functions of the analog circuit blocks using a plurality of multiplexer (MUX) circuits including port MUX circuits coupled between the analog circuit blocks and ports that provide signal connections for the chip.

16. The method of claim 15, wherein:

the programmable interconnect is further configurable to enable any of the analog circuit blocks to be connected to at least one port that provides a signal connection point to the chip.

17. The method of claim 15, wherein:

the programmable interconnect is further configurable to enable any of the digital circuit blocks to be interconnected to combine digital functions of the digital circuit blocks.

18. The method of claim 15, wherein:

the programmable interconnect is configurable to enable at least two analog circuit blocks to be coupled in series.

19. The method of claim 15, wherein:

the programmable interconnect is further configurable to enable any of the analog circuit blocks to be connected to the at least one digital circuit block.