Nano-sense amplifier
First Claim
Patent Images
1. A sense amplifier (nSA) of a series of cells (Ci, Cj) of a memory, including:
- a writing stage comprising a CMOS inverter (T1-T2), the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline (LBL) addressing the cells of said series, anda reading stage comprising a sense transistor (T3), the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter;
wherein each of the transistors has a back control gate formed in the base substrate below the channel and capable of being biased in order to modulate the threshold voltage of the transistor.
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Abstract
A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline addressing the cells of the series, and a reading stage that includes a sense transistor, the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter.
87 Citations
22 Claims
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1. A sense amplifier (nSA) of a series of cells (Ci, Cj) of a memory, including:
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a writing stage comprising a CMOS inverter (T1-T2), the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline (LBL) addressing the cells of said series, and a reading stage comprising a sense transistor (T3), the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter; wherein each of the transistors has a back control gate formed in the base substrate below the channel and capable of being biased in order to modulate the threshold voltage of the transistor. - View Dependent Claims (2, 3, 4, 5, 12, 13, 14, 15, 16, 18, 19, 20, 21, 22)
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6. A sense amplifier (nSA) of a series of cells (Ci, Cj) of a memory, including:
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a writing stage comprising a CMOS inverter (T1-T2), the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline (LBL) addressing the cells of said series, and a reading stage comprising a sense transistor (T3), the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter, wherein the reading stage comprises an additional transistor (T4) complementary to the sense transistor, the additional transistor and the sense transistor forming a CMOS inverter, the input of which is connected to the output of the reading stage and the output of which is connected to the input of the inverter of the writing stage. - View Dependent Claims (7, 8, 9, 17)
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10. A main sense amplifier (MSA) intended to be connected via a main bitline (MBL) to a plurality of sense amplifiers (nSA) of a series of cells (Ci, Cj) of a memory, including a writing stage comprising a CMOS inverter (T1-T2), the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline (LBL) addressing the cells of said series, and a reading stage comprising a sense transistor (T3), the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter, the MSA comprising means for amplifying the signal (T6-T10) delivered by a cell during a reading operation, and a switchable high impedance inverter stage (HZ1) for sending back the amplified signal onto the main bitline following the reading operation.
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11. A sense amplifier (nSA) including:
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a writing stage comprising a CMOS inverter (T1-T2), the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local line, and a reading stage comprising a sense transistor (T3), the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter; wherein one or more transistors of the writing stage and of the reading stage are independent double gate transistors; wherein each of the transistors has a back control gate formed in the base substrate below the channel and capable of being biased in order to modulate the threshold voltage of the transistor.
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Specification