Memory board with self-testing capability

• US 8,359,501 B1
• Filed: 07/14/2011
• Issued: 01/22/2013
• Est. Priority Date: 04/14/2008
• Status: Active Grant

• Current Assignee: Netlist, Inc.
• Original Assignee: Netlist, Inc.
• Inventors: Lee, Hyun, Bhakta, Jayesh R., Choi, Soonju
• Primary Examiner(s): Chung, Phung M
• Application Number:
  US13/183,253
• Time in Patent Office: 558 Days
• Field of Search: 714/718, 714/719, 714/736, 714/733, 714/734, 714/738, 714/819, 365/201
• US Class Current: 714/719
• CPC Class Codes: G11C 29/10 Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

A self-testing memory module includes a printed circuit board configured to be operatively coupled to a memory controller of a computer system and includes a plurality of memory devices on the printed circuit board, each memory device of the plurality of memory devices comprising data, address, and control ports. The memory module also includes a control module configured to generate address and control signals for testing the memory devices. The memory module includes a data module comprising a plurality of data handlers. Each data handler is operable independently from each of the other data handlers of the plurality of data handlers. Each data handler is operatively coupled to a corresponding plurality of the data ports of one or more of the memory devices and is configured to generate data for writing to the corresponding plurality of data ports.

Claims

1. A memory system configured to be operatively coupled to a memory controller of a computer system, the memory system comprising:

a plurality of memory chips;

a plurality of data handlers configured to be operated independently from one other, wherein one or more data handlers of the plurality of data handlers are configured to generate data for writing to a corresponding one or more memory chips of the plurality of memory chips;

a control circuit configured to generate address and control signals, wherein the memory system is configured to test the one or more memory chips using the address and control signals generated by the control circuit and using the data generated by the one or more data handlers.

2. The memory system of claim 1, wherein each of the one or more memory chips comprises address and control ports configured to receive the address and control signals generated by the control circuit and data ports configured to receive the data generated by the one or more data handlers.

3. The memory system of claim 2, wherein the one or more data handlers are positioned closer to the data ports of the one or more memory chips than to data ports of other memory chips of the plurality of memory chips.

4. The memory system of claim 1, wherein the memory system comprises at least two physically separate integrated circuit packages, wherein each of the at least two physically separate integrated circuit packages comprises at least one data handler of the plurality of data handlers.

5. The memory system of claim 1, wherein the memory system is configured to test the one or more memory chips by writing the data generated by the one or more data handlers to one or more memory locations of the one or more memory chips.

6. The memory system of claim 5, wherein the one or more data handlers are further configured to receive data from the one or more memory chips and to identify failures in the operation of the one or more memory chips by verifying that data received from the one or more memory locations of the one or more memory chips corresponds to the data generated and written by the one or more data handlers to the one or more memory locations of the one or more memory chips.

7. The memory system of claim 6, wherein the one or more data handlers are further configured to verify that the data read from the one or more memory locations of the one or more memory chips corresponds to the data generated and written by the one or more data handlers to the one or more memory locations of the one or more memory chips without storing a copy of the data generated and written by the one or more data handlers.

8. The memory system of claim 6, wherein the one or more data handlers are configured to calculate comparison data and to compare the comparison data to the data read from the one or more memory locations of the one or more memory chips.

9. The memory system of claim 5, wherein the control circuit is further configured to store memory addresses associated with failures in the operation of the one or more memory locations of the one or more memory chips.

10. The memory system of claim 5, wherein the memory system is further configured to store data associated with failures in the operation of the one or more memory locations of the one or more memory chips.

11. The memory system of claim 1, wherein the data generated by the one or more data handlers for writing to the one or more memory chips comprises cyclic data.

12. The memory system of claim 11, wherein the one or more data handlers are further configured to calculate comparison data based on the cyclic data and to compare the comparison data to data read from the one or more memory locations of the one or more memory chips.

13. The memory system of claim 1, wherein the one or more data handlers are further configured to calculate comparison data based on a current read address and to compare the comparison data to data read from the one or more memory locations of the one or more memory chips.

14. The memory system of claim 1, wherein the one or more circuits are further configured to write data to the one or more memory chips by selectively inputting to the one or more memory chips either data signals from the memory controller of the computer system or data signals from the one or more circuits.

15. The memory system of claim 1, wherein the control circuit is further configured to selectively input to the address and control ports of the one or more memory chips either the address and control signals from the memory controller of the computer system or the address and control signals from the control circuit.

16. A method of operating a memory system configured to be operatively coupled to a memory controller of a computer system, the memory system having a plurality of memory chips, the method comprising:

operating a plurality of data handlers independently from one another to generate and transmit data to one or more memory locations of one or more memory chips of the plurality of memory chips;

operating a control circuit to generate address and control signals; and

testing the one or more memory locations of the one or more memory chips using the address and control signals generated by the control circuit and using the data generated by the plurality of data handlers.

17. The method of claim 16, further comprising:

receiving, by the plurality of data handlers, data from the one or more memory locations of the one or more memory chips; and

verifying that the data received from the one or more memory locations of the one or more memory chips corresponds to the data transmitted to the one or more memory locations of the one or more memory chips.

18. The method of claim 17, wherein said verifying is performed without storing a copy of the data transmitted to the one or more memory locations of the one or more memory chips.

19. The method of claim 17, wherein said verifying comprises:

calculating comparison data; and

comparing the comparison data to the data received from the one or more memory locations of the one or more memory chips.

20. The method of claim 17, wherein the data transmitted to the one or more memory locations of the one or more memory chips comprises cyclic data.