Memory board with self-testing capability

CAFC
  • US 8,359,501 B1
  • Filed: 07/14/2011
  • Issued: 01/22/2013
  • Est. Priority Date: 04/14/2008
  • Status: Active Grant
First Claim
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1. A memory system configured to be operatively coupled to a memory controller of a computer system, the memory system comprising:

  • a plurality of memory chips;

    a plurality of data handlers configured to be operated independently from one other, wherein one or more data handlers of the plurality of data handlers are configured to generate data for writing to a corresponding one or more memory chips of the plurality of memory chips;

    a control circuit configured to generate address and control signals, wherein the memory system is configured to test the one or more memory chips using the address and control signals generated by the control circuit and using the data generated by the one or more data handlers.

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