Precise resistor on a semiconductor device

• US 8,361,848 B2
• Filed: 04/29/2010
• Issued: 01/29/2013
• Est. Priority Date: 04/29/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Da-Yuan, Yeh, Matt
• Primary Examiner(s): Nguyen, Cuong Q
• Assistant Examiner(s): Gebreyesus, Yosef
• Application Number:
  US12/770,166
• Publication Number:
  US 20110266637A1
• Time in Patent Office: 1,006 Days
• Field of Search: 438/171, 438/190, 438/210, 438/238, 438/329, 438/330, 438/332, 438/381, 438/382, 438/383, 438/384, 438/488, 438/491, 438/764, 438/208, 438/912, 438/510, 438/514, 257/359, 257/380, 257/385, 257/538, 257/581, 257/904, 257E29325-E29346
• US Class Current: 438/171
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A method includes forming a polysilicon layer on a substrate; and patterning the polysilicon layer to form a polysilicon resistor and a polysilicon gate. A first ion implantation is performed on the polysilicon resistor to adjust electric resistance of the polysilicon resistor. A second ion implantation is performed on a top portion of the polysilicon resistor such that the top portion of the polysilicon resistor has an enhanced etch resistance. An etch process is then used to remove the polysilicon gate while the polysilicon resistor is protected by the top portion.

Claims

1. A method of making an integrated circuit, the method comprising:

forming a polysilicon layer on a substrate;

patterning the polysilicon layer to form a polysilicon resistor and a polysilicon gate;

forming a protective layer over the polysilicon gate;

performing a first ion implantation to the polysilicon layer to adjust electric resistance of the polysilicon resistor, wherein the polysilicon gate is covered by the protective layer during performance of the first ion implantation;

performing a second ion implantation to a top portion of the polysilicon resistor such that the top portion has an enhanced etch resistance; and

performing an etch process to remove the polysilicon gate while the polysilicon resistor is protected by the implanted top portion.

2. The method of claim 1, further comprising forming a high-k dielectric material layer on the substrate.

3. The method of claim 1, wherein the performing the second ion implantation includes implanting the polysilicon resistor using one of boron (B) and boron fluoride (BF2).

4. The method of claim 1, wherein the performing the first ion implantation includes implanting the polysilicon resistor using one of BF2 and B.

5. The method of claim 1, wherein the performing the second ion implantation includes implanting doping species to the top portion having a thickness less than about 5 nm.

6. The method of claim 5, wherein the top portion of the polysilicon resistor includes boron as dopant with a doping concentration greater than about 10¹⁹/cm³.

7. The method of claim 1, further comprising:

forming source and drain in the substrate and interposed by the polysilicon gate;

forming a metal layer in a gate trench formed after the performing an etch process;

filling the gate trench with a conductive layer on the metal layer; and

performing a chemical mechanical polishing process to remove excessive portions of the metal layer and the conductive layer.

8. The method of claim 7, wherein the source and drain are n-type dopant, and the metal layer has a work function less than 4.2 eV.

9. The method of claim 7, wherein the source and drain are p-type dopant, the metal layer has a work function greater than 5.2 eV.

10. The method of claim 1, wherein the performing a first ion implantation to the polysilicon layer includes performing the first ion implantation to the polysilicon layer before the patterning the polysilicon layer.

11. The method of claim 1, further comprising, after the performing a second ion implantation and before the performing an etch process:

forming an inter-level dielectric (ILD) layer on the semiconductor substrate; and

performing a first chemical mechanical polishing process to etch back the ILD layer.

12. A method comprising:

forming a polysilicon resistor and a polysilicon gate on a semiconductor substrate;

performing a first ion implantation to the polysilicon resistor to adjust electric resistance of the polysilicon resistor, wherein the polysilicon gate is covered by a first patterned material layer during performance of the first ion implantation;

performing a second ion implantation to the polysilicon gate to form source and drain regions in the semiconductor substrate that are adjacent the polysilicon gate, wherein the polysilicon resistor is covered by a second patterned material layer during performance of the second ion implantation; and

performing a third ion implantation to the polysilicon resistor such that a top portion of the polysilicon resistor has an enhanced etch resistance, wherein the polysilicon gate is covered by a third patterned material layer during performance of the third ion implantation.

13. The method of claim 12, wherein the first, second, and third material layers are different from each other.

14. The method of claim 12, wherein the first, second, and third ion implantations are different from each other.

15. The method of claim 12, wherein performing the first ion implantation includes implanting the polysilicon resistor using boron (B) and wherein performing the first ion implantation includes implanting the polysilicon resistor using boron fluoride (BF2).

16. The method of claim 12, wherein performing the second ion implantation to the polysilicon gate to form source and drain regions in the semiconductor substrate that are adjacent the polysilicon gate occurs after performing the first ion implantation and before performing the third ion implantation.

17. The method of claim 12, further comprising removing the first patterned material layer covering the polysilicon gate prior to performing the third ion implantation.

18. The method of claim 12, performing an etch process to remove the polysilicon gate while the polysilicon resistor is protected by the implanted top portion.

19. A method comprising:

forming a polysilicon resistor and a polysilicon gate on a semiconductor substrate;

forming a first patterned material layer over the polysilicon gate;

performing a first ion implantation to the polysilicon resistor to adjust electric resistance of the polysilicon resistor, wherein the polysilicon gate is covered by the first patterned material layer during performance of the first ion implantation;

forming a second patterned material layer over the polysilicon gate, the second patterned material layer being different than the first patterned material layer; and

after forming the second patterned material layer over the polysilicon gate, performing a second ion implantation to the polysilicon resistor such that a top portion of the polysilicon resistor has an enhanced etch resistance, wherein the polysilicon gate is covered by the second patterned material layer during performance of the second ion implantation.

20. The method of claim 19, further comprising removing the first patterned material layer prior to performing the second ion implantation.