Soft error correction method, memory control apparatus and memory system

• US 8,365,031 B2
• Filed: 10/05/2009
• Issued: 01/29/2013
• Est. Priority Date: 03/17/2005
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Suzuki, Kenji, Honda, Yasufumi, Koguchi, Takashi
• Primary Examiner(s): Baderman, Scott
• Assistant Examiner(s): Arcos, Jeison C
• Application Number:
  US12/573,491
• Publication Number:
  US 20100023827A1
• Time in Patent Office: 1,212 Days
• Field of Search: 702/182, 702/183, 702/132, 700/29, 700/30, 714/25, 714/47, 714/52, 714/6.1
• US Class Current: 714/747
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution

Abstract

A soft error correction method is for a memory system having memory access controllers accessing memories for storing byte-sliced data in cycle synchronism, and a system controller receiving a memory access from an arbitrary one of MPUs and issuing a memory address to the memory access controllers. When a correctable error is detected in data read from one memory, an error address where the error was detected is held within a memory access controller, and an error notification is made to the system controller from the memory access controller. In response to the error notification, the memory access controller holds the error address from the system controller without intervention from the MPUs, and reads, corrects and rewrites the data to the error address.

Claims

1. A memory control apparatus for a memory system having a plurality of memories configured to store byte-sliced data, a plurality of memory access controllers provided in correspondence with the plurality of memories and respectively configured to make an access in cycle synchronism with respect to a corresponding one of the plurality of memories, and a system controller configured to issue a read request with respect to the plurality of memory access controllers, comprising:

a first circuit configured to hold an error address where a correctable error is detected when the correctable error is detected in data read from one of the plurality of memories;

a second circuit configured to make an error notification with respect to the system controller;

a third circuit configured to receive an error correction request and a dummy read address from the system controller; and

a fourth circuit configured to read the data from the error address and perform a soft error correction when the first circuit holds error address and the error correction request is received by the third circuit, and to read the data from the dummy read address received by the third circuit and write back the read data when the first circuit does not hold the error address.

2. The memory control apparatus as claimed in claim 1, wherein the second circuit makes the error notification via a bus that sends a status from the system controller to the one of the plurality of memory access controllers.

3. A memory system comprising:

a plurality of memories configured to store byte-sliced data;

a plurality of memory access controllers, provided in correspondence with the plurality of memories, and respectively configured to make an access in cycle synchronism with respect to a corresponding one of the plurality of memories; and

a system controller configured to issue a read request with respect to each of the plurality of memory access controller, based on a memory access request,

wherein each of the plurality of memory access controllers includes

a first circuit configured to hold an error address where a correctable error is detected when the correctable error is detected in data read from one of the plurality of memories,

a second circuit configured to make an error notification with respect to the system controller,

a third circuit configured to receive an error correction request and a dummy read address from the system controller, and

a fourth circuit configured to read the data from the error address and perform a soft error correction when the first circuit holds error address and the error correction request is received by the third circuit, and to read the data from the dummy read address received by the third circuit and write back the read data when the first circuit does not hold the error address, and

wherein the system controller includes

a fifth circuit configured to send the error correction request and the dummy read address to each of the plurality of memory access controllers when the error notification is received from one of the plurality of memory access controllers.

4. The memory system as claimed in claim 3, wherein the second circuit makes the error notification via a bus that sends a status from the system controller to the one of the plurality of memory access controllers.

5. A soft error correction method for a memory system having a plurality of memory access controllers that are respectively configured to access one of a plurality of memories that store byte-sliced data in cycle synchronism with each other, and a system controller configured to receive a memory access from one of a plurality of MPUs and to issue a read request with respect to each of the plurality of memory access controllers, comprising:

when one of the plurality of memory access controllers detects a correctable error in data read from one of the plurality of memories, holding an error address where the error is detected and sending an error notification from said one of the plurality of memory access controllers to the system controller;

responsive to the error notification from said one of the plurality of memory access controllers, sending an error correction request and a dummy read address from the system controller to each of the plurality of memory access controllers;

when said one of the plurality of memory access controllers receives the error correction request, reading the data from the error address and performing a soft error correction by said one of the plurality of memory access controllers; and

reading the data from the dummy read address and writing back the read data by each of the plurality of memory access controllers not holding the error address.

6. The soft error correction method as claimed in claim 5, wherein the second circuit makes the error notification via a bus that sends a status from the system controller to the one of the memory access controllers.