Single-chip wireless tranceiver

• US 8,369,388 B2
• Filed: 12/21/2007
• Issued: 02/05/2013
• Est. Priority Date: 06/15/2007
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Hammerschmidt, Joachim S., Behzad, Arya Reza, Carter, Keith Andrews, Furrer, Simeon, Gaikwad, Rohit Vijay, Trachewsky, Jason Alexander, Bagchi, Amit, Moorti, Rajendra Tushar, Kodavati, Venkateswara Rao
• Primary Examiner(s): Liu, Shuwang
• Assistant Examiner(s): TAYONG, HELENE E
• Application Number:
  US12/004,406
• Publication Number:
  US 20080310487A1
• Time in Patent Office: 1,873 Days
• Field of Search: 375/219, 375/354, 375/295, 375/260, 375/316, 370/73, 370/276, 710/1, 455/78, 455/102, 455/73
• US Class Current: 375/219
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H04B 7/0413 MIMO systems

Abstract

Embodiments of a wireless transceiver are provided. Embodiments can be used in multiple-input-multiple-output (MIMO) wireless transceivers. In an embodiment, radio control signal bundles are provided as direct parallel interconnects between digital signal processing modules and the radio module of the wireless transceiver to enable a precise low-latency control of radio functions. In another embodiment, a separate physical line is provided to control each radio setting of the radio module, thereby enabling simultaneous real-time control of any number of radio settings. In a further embodiment, the various digital and analog components of the wireless transceiver are integrated within a single chip of the same process technology.

Claims

1. An integrated circuit (IC), comprising:

a multiple-input-multiple-output (MIMO) radio module, including a plurality of transmitter and receiver units;

a MIMO digital signal processing (DSP) module;

a host processor interface that interfaces between said MIMO DSP module and a host processor; and

a plurality of radio control signal bundles that connect said MIMO DSP module and said MIMO radio module, said plurality of radio control signal bundles including,

a plurality of transmit radio control signal bundles, each of said transmit radio control signal bundles dedicated to a respective transmitter unit of said MIMO radio module and comprising transmit control signal lines, wherein said respective transmitter unit includes a first plurality of stages including a frequency-up conversion stage and a first gain amplification stage, and wherein each of said transmit control signal lines is dedicated to control a respective stage of the first plurality of stages of said respective transmitter unit;

a plurality of receive radio control signal bundles, each of said receive radio control signal bundles dedicated to a respective receiver unit of said MIMO radio module and comprising receive control signal lines, wherein said respective receiver unit includes a second plurality of stages including a frequency down-conversion stage and a second gain amplification stage, and wherein each of said receive control signal lines is dedicated to control a respective stage of the second plurality of stages of said respective receiver unit;

wherein said transmit and receive control signal lines enable said MIMO DSP module to control simultaneously any number of said first plurality of stages and second plurality of stages of said respective transmitter and receiver units.

2. The IC of claim 1, wherein said MIMO DSP module comprises a MIMO Transmit module to generate and transmit a plurality of transmit data signals to respective ones of said transmitter units of said MIMO radio module.

3. The IC of claim 1, wherein said MIMO DSP module comprises a MIMO Receive module to receive a plurality of receive data signals from respective ones of said receiver units of said MIMO radio module.

4. The IC of claim 2, further comprising a plurality of digital-to-analog converters (DACs) coupled between said MIMO Transmit module and said respective ones of said transmitter units.

5. The IC of claim 3, further comprising a plurality of analog-to-digital converters (ADCs) coupled between said MIMO Receive module and said respective ones of said receiver units.

6. The IC of claim 1, wherein each of said respective transmitter unit further comprises at least one of one or more variable bandwidth filtering stages;

and circuitry to selectively enable/disable said frequency up-conversion, amplification, and filtering stages, and

wherein said respective receiver unit further comprises at least one of one or more variable bandwidth filtering stages; and

circuitry to selectively enable/disable said frequency down-conversion, amplification, and filtering stages.

7. The IC of claim 6, further comprising a synthesizer module to generate and provide frequency conversion signals to said frequency up-conversion stages and frequency down-conversion stages.

8. The IC of claim 1, wherein said MIMO radio module and said MIMO DSP module are implemented using the same process technology.

9. The IC of claim 1, wherein the IC comprises CMOS technology.

10. The IC of claim 1, wherein said MIMO DSP module is positioned between said MIMO radio module and said host processor interface.

11. The IC of claim 1, wherein said MIMO radio module, said MIMO DSP module, and said host processor interface are positioned to provide a maximum or near maximum distance between analog components of said MIMO radio module and high-speed digital components of said host processor interface.

12. The IC of claim 1, wherein said MIMO radio module, said MIMO DSP module, and said host processor interface are positioned to minimize lengths of signal interconnects that carry said plurality of radio control signal bundles.

13. The IC of claim 1, wherein said MIMO radio module, said MIMO DSP module, and said host processor interface are positioned to increase effective heat drain-off area of said MIMO radio module.

14. The IC of claim 1, wherein each of said transmitter units comprises an integrated power amplifier (PA).

15. The IC of claim 1, wherein said plurality of radio control signal bundles enable real-time control of said plurality of transmitter and receiver units of said MIMO radio module.

16. The IC of claim 1, wherein said plurality of radio control signal bundles are provided over direct parallel interconnects between said MIMO DSP module and said MIMO radio module.

17. The IC of claim 1, wherein said plurality of radio control signal bundles are provided over separate interconnects between said MIMO DSP module and said MIMO radio module.

18. The IC of claim 1, wherein each of said transceiver units comprises an integrated transmit/receive (T/R) switch.

19. The IC of claim 1, wherein each of said transceiver units comprises an integrated diplexer.

20. The IC of claim 1, wherein said radio module is a single-band radio.

21. The 1C of claim 1, wherein said radio module is a dual-band radio.

22. The IC of claim 1, wherein the number of transmitter units and corresponding radio control signal bundles is two, and the number of receiver units and corresponding radio control signal bundles is one.

23. The IC of claim 1, wherein the number of transmitter units and corresponding radio control signal bundles is one, and the number of receiver units and corresponding radio control signal bundles is two.

24. The IC of claim 1, wherein the number of transmitter units and corresponding radio control signal bundles is two, and the number of receiver units and corresponding radio signal control bundles is two.

25. The IC of claim 1, wherein the number of transmitter units and corresponding radio control signal bundles is two, and the number of receiver units and corresponding radio control signal bundles is three.

26. The IC of claim 1, wherein the number of transmitter units and corresponding radio control signal bundles is three, and the number of receiver units and corresponding radio control signal bundles is three.

27. The IC of claim 1, wherein the number of transmitter units and corresponding radio control signal bundles is three, and the number of receiver units and corresponding radio control signal bundles is four.

28. The IC of claim 1, wherein the number of transmitter units and corresponding radio control signal bundles is four, and the number of receiver units and corresponding radio control signal bundles is four.

29. The IC of claim 1, wherein the number of transmitter units and corresponding radio control signal bundles is four, and the number of receiver units and corresponding radio control signal bundles is two.

30. The IC of claim 1, wherein the number of transmitter units and corresponding radio control signal bundles is four, and the number of receiver units and corresponding radio control signal bundles is three.

31. The IC of claim 1, wherein said MIMO DSP module comprises a control logic module that drives said plurality of radio control signal bundles.

32. An integrated circuit (IC), comprising:

a multiple-input-multiple-Output (MIMO) radio module, including a plurality of transmitter and receiver units, a MIMO digital signal processing (DSP) module;

an embedded host processor, coupled to said MIMO DSP module; and

a plurality of radio control signal bundles that connect said MIMO DSP module and said MIMO radio module, said plurality of radio control signal bundles including,

a plurality of transmit radio control signal bundles, each of said transmit radio control signal bundles dedicated to a respective transmitter unit of said MIMO radio module and comprising transmit control signal lines, wherein said respective transmitter unit includes a first plurality of stages, including a frequency-up conversion stage and a first gain amplification stage, and wherein each of said transmit control signal lines is dedicated to control a respective stage of the first plurality of stages of said respective transmitter unit;

a plurality of receive radio control signal bundles, each of said receive radio control signal bundles dedicated to a respective receiver unit of said MIMO radio module and comprising receive control signal lines, wherein said respective receiver unit includes a second plurality of stages including a frequency down-conversion stage and a second gain amplification stage, and wherein each of said receive control signal lines is dedicated to control a respective stage of the second plurality of stages of said respective receiver unit;

wherein said transmit and receive control signal lines enable said MIMO DSP module to control simultaneously any number of said first plurality of stages and second plurality of stages of said plurality of respective transmitter and receiver units.

33. An integrated circuit (IC), comprising:

a multiple-input-multiple-output (MIMO) radio module, including a plurality of transmitter units;

a MIMO digital signal processing (DSP) module;

a host processor interface that interfaces between said MIMO DSP module and a host processor; and

a plurality of radio control signal bundles that connect said MIMO DSP module and said MIMO radio module, said plurality of radio control signal bundles including, a plurality of transmit radio control signal bundles, each of said transmit radio control signal bundles dedicated to a respective transmitter unit of said MIMO radio module and comprising transmit control signal lines, wherein said respective transmitter unit includes a plurality of stages, including a frequency-up conversion stage and a first gain amplification stage, and wherein each of said transmit control signal lines is dedicated to control a respective stage of the plurality of stages of said respective transmitter unit;

wherein said transmit control signal lines enable said MIMO DSP module to control simultaneously any number of said plurality stages of said respective transmitter unit.