Non-volatile semiconductor storage device and method of manufacturing the same

• US 8,372,720 B2
• Filed: 12/09/2008
• Issued: 02/12/2013
• Est. Priority Date: 12/11/2007
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Fukuzumi, Yoshiaki, Katsumata, Ryota, Kidoh, Masaru, Kito, Masaru, Tanaka, Hiroyasu, Komori, Yosuke, Ishiduki, Megumi, Aochi, Hideaki
• Primary Examiner(s): Lee, Calvin
• Assistant Examiner(s): Harrison, Monica D
• Application Number:
  US12/679,991
• Publication Number:
  US 20100207195A1
• Time in Patent Office: 1,526 Days
• Field of Search: 257/326, 257/E29.309, 257/E21.423, 438/287
• US Class Current: 438/287
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

Claims

1. A method of manufacturing a non-volatile semiconductor storage device having a plurality of memory strings in each of which a plurality of electrically rewritable memory cells are connected in series, the method comprising:

forming a first conductive layer on a substrate through a first insulation layer;

forming grooves extending in a first direction that is in parallel with the substrate in the first conductive layers;

forming a plurality of second conductive layers on upper layers of the first conductive layers through second insulation layers;

forming first through holes so that the first through holes pass through the second conductive layers and the second insulation layers as well as are aligned in vicinities of both ends in the first direction of the grooves;

forming charge storage layers to the grooves and side surfaces facing the first through holes; and

forming first semiconductor layers to side surfaces of the charge storage layers.

2. The method of manufacturing a non-volatile semiconductor storage device according to claim 1, wherein

each of the first semiconductor layers is arranged to have a pair of columnar portions extending in a vertical direction with respect to a substrate, and

the method further comprises dividing the second conductive layers for each of the respective columnar portions adjacent to each other in the first direction.

3. The method of manufacturing a non-volatile semiconductor storage device according to claim 2, further comprising dividing the second conductive layers so that the first semiconductor layers arranged in the first direction share the second conductive layers in the columnar portions.

4. The method of manufacturing a non-volatile semiconductor storage device according to claim 2, further comprising dividing each of the second conductive layers into a pair of comb shapes facing in a second direction orthogonal to the first direction and to the vertical direction, wherein

the second conductive layers are formed to have projecting portions extending in the second direction,

the projecting portion of one of the second conductive layers is formed to surround the columnar portion of one of the first semiconductor layers, and

the projecting portion of the other second conductive layer is formed to surround the columnar portion of the other first semiconductor layer.

5. The method of manufacturing a non-volatile semiconductor storage device according to claim 1, further comprising forming third conductive layers on the upper surfaces of the first conductive layers, wherein

the second conductive layers are formed on upper layers of the third conductive layers, and

the first through holes are formed to pass through the third conductive layers, the second conductive layers, and the second insulation layers.

6. The method of manufacturing a non-volatile semiconductor storage device according to claim 1, wherein the first semiconductor layers are formed to have hollow portions.

7. The method of manufacturing a non-volatile semiconductor storage device according to claim 6, further comprising forming internal dielectric layers so that the hollow portions are filled with the internal dielectric layers.

8. The method of manufacturing a non-volatile semiconductor storage device according to claim 1, further comprising:

forming fourth conductive layers on upper layers of the second conductive layers at positions where the fourth conductive layers are aligned with the upper surfaces of the first semiconductor layers;

forming second through holes so as to pass through the fourth conductive layers;

forming gate insulation layers on side surfaces facing the second through holes; and

forming second semiconductor layers so that the second through holes are filled with the second semiconductor layers.