Semiconductor device and delay locked loop circuit thereof
First Claim
1. A semiconductor device, comprising:
- a first phase detector configured to detect a phase of a second clock by comparing the phase of the second clock with a phase of a first clock;
a second phase detector configured to detect a phase of a clock obtained by delaying the second clock by a delay amount by comparing the phase of the delayed second clock with the phase of the first clock;
a third phase detector configured to detect the phase of the second clock by comparing the phase of the second clock with a phase of a clock obtained by delaying the first clock by the delay amount; and
a phase difference detection signal generator configured to set a logic level of a phase difference detection signal corresponding to a phase difference between the first and second clocks in response to signals respectively outputted from the first to third phase detectors, detect that the phase of the first or second clock is changed by a phase corresponding an amount two times greater than the delay amount, and change the logic level of the phase difference detection signal in response to the detected result.
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Abstract
A semiconductor device includes a first phase detector for detecting a phase of a second clock by comparing the phase of the second clock with the phase of the first clock, a second phase detector for detecting a phase of a clock obtained by delaying the second clock by a set delay amount, a third phase detector for detecting the phase of the second clock by delaying the first clock by the set delay amount, and a phase difference detection signal generator for setting a logic level of a phase difference detection signal corresponding to a phase difference between the first and second clocks detecting that the phase of the first or second clock is changed, and change the logic level of the phase difference detection signal.
19 Citations
12 Claims
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1. A semiconductor device, comprising:
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a first phase detector configured to detect a phase of a second clock by comparing the phase of the second clock with a phase of a first clock; a second phase detector configured to detect a phase of a clock obtained by delaying the second clock by a delay amount by comparing the phase of the delayed second clock with the phase of the first clock; a third phase detector configured to detect the phase of the second clock by comparing the phase of the second clock with a phase of a clock obtained by delaying the first clock by the delay amount; and a phase difference detection signal generator configured to set a logic level of a phase difference detection signal corresponding to a phase difference between the first and second clocks in response to signals respectively outputted from the first to third phase detectors, detect that the phase of the first or second clock is changed by a phase corresponding an amount two times greater than the delay amount, and change the logic level of the phase difference detection signal in response to the detected result. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A delay locked loop (DLL) circuit, comprising:
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a phase comparator configured to compare phases of a source clock and a feedback clock and generate a phase comparison signal and a phase difference detection signal corresponding to the compared result; a clock delay configured to delay the source clock through a variable delay line and output the delayed source clock as a delay locked clock, wherein the variable delay line controls the variation width of a delay amount in response to the phase difference detection signal and controls the variation direction of the delay amount in response to the phase comparison signal; and a replica modeling configured to delay the delay locked clock by a delay amount obtained by modeling an input delay path of the source clock and an output delay path of the delay locked clock and output the delayed delay locked clock as the feedback clock, wherein the phase comparator comprises; a first phase detector configured to detect the phase of the feedback clock by comparing the phase of the second clock with the phase of the source clock; a second phase detector configured to detect a phase of a clock obtained by delaying the feedback clock by a set delay amount by comparing the phase of the delayed second clock with the phase of the source clock; a third phase detector configured to detect the phase of the feedback clock by comparing the phase of the second clock with a phase of a clock obtained by delaying the source clock by the set delay amount; and a phase difference detection signal generator configured to set a logic level of the phase difference detection signal corresponding to a phase difference between the source clock and the feedback clock in response to signals respectively outputted from the first to third phase detectors, detect that the phase of the feedback clock is changed by a phase corresponding an amount two times greater than the delay amount, and change the logic level of the phase difference detection signal in response to the detected result. - View Dependent Claims (8, 9, 10, 11, 12)
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Specification