Frequency synthesis and synchronization for LED drivers

• US 8,373,643 B2
• Filed: 10/03/2008
• Issued: 02/12/2013
• Est. Priority Date: 10/03/2008
• Status: Expired due to Fees

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Zhao, Bin, Kameya, Andrew M., Lee, Victor K.
• Primary Examiner(s): HARRIS, DOROTHY H
• Application Number:
  US12/244,796
• Publication Number:
  US 20100085295A1
• Time in Patent Office: 1,593 Days
• Field of Search: 345/102
• US Class Current: 345/102
• CPC Class Codes: G09G 2320/064 by time modulation of the brightness of the illumination source
• CPC Class Codes: G09G 3/3406 Control of illumination source illumination devices structurally associated with liquid crystal cells G02F1/1336

Abstract

A PWM generation module generates a PWM data signal used to control a light emitting diode (LED) driver for one or more strings of LEDs of a display device. The PWM data signal is synchronized with the frame boundaries of the video content being displayed. The PWM generation module can configure the PWM data signal such that a new PWM cycle is initiated at the start of each successive frame, and further whereby those PWM cycles that would be prematurely terminated at frame boundaries are instead driven at a constant reference level until the frame boundary. With this configuration, a substantially linear average light intensity can be achieved across frames, thereby reducing or eliminating display distortion that is often present in other PWM cycle synchronization techniques. The PWM generation module can use a self-learning process to make adjustments to the expected number of completeable PWM cycles per frame in response to dynamic changes in the frame rate, PWM frequency, or other related display parameters.

Claims

1. A method comprising:

generating a pulse width modulation (PWM) data signal, the PWM data signal comprising;

a first sequence of PWM cycles having a first predetermined duty ratio, an initial PWM cycle of the first sequence being synchronized to a start of a display of a first frame of a video data at a display device, wherein the PWM data signal transitions from a first level to a second level during each PWM cycle;

a first portion of the PWM data signal starting in the first frame following the first sequence of PWM cycles and terminating responsive to a start of display of a second frame of the video data at the display device, the second frame following the first frame, the first portion having a level matching the second level for the duration of the first portion, the duration of the first portion different than the duration of a PWM cycle of the first sequence of PWM cycles; and

a second sequence of PWM cycles, an initial PWM cycle of the second sequence being synchronized to the start of the second frame; and

providing the PWM data signal to a light emitting diode (LED) driver for control of one or more LEDs of the display device.

2. The method of claim 1, wherein generating the PWM data signal further comprises generating the PWM data signal comprising:

a second portion of the PWM data signal starting in the second frame following the second sequence of PWM cycles and terminating responsive to a start of a display of a third frame following the second frame, the second portion having a level matching the second level for the duration of the second portion, the duration of the second portion different than the duration of a PWM cycle of the second sequence of PWM cycles, the second sequence of PWM cycles having a second predetermined duty ratio.

3. The method of claim 2, wherein generating the PWM data signal comprises:

determining a first number of completeable PWM cycles expected to occur during the display of the first frame;

responsive to the start of the display of the first frame, driving the first sequence of PWM cycles on the PWM data signal by driving PWM cycles having the first predetermined duty ratio and incrementing a first count for each completed PWM cycle of the first sequence until the first count is equal to the first number of completeable PWM cycles;

responsive to the first count being equal to the first number of completeable PWM cycles, driving the PWM data signal at the second level until detecting the start of the display of the second frame;

responsive to determining the duration of the first portion exceeds the duration of the PWM cycle of the first sequence of PWM cycles, increasing a second number of completeable PWM cycles expected to occur during the display of the second frame; and

responsive to determining the duration of the second portion is less than the duration of the cycle of the second sequence of PWM cycles, maintaining the second number of completeable PWM cycles at the same number.

4. The method of claim 3, further comprising:

responsive to the start of the display of the second frame, driving the second sequence of PWM cycles on the PWM data signal by driving PWM cycles having the second predetermined duty ratio and incrementing a second count for each driven PWM cycle until the second count is equal to the second number of completeable PWM cycles; and

responsive to the second count being equal to the second number of completeable PWM cycles expected to occur during the display of the second frame, driving the PWM data signal at the second level until the start of the display of the third frame.

5. The method of claim 2, wherein generating the PWM data signal comprises:

determining a first number of completeable PWM cycles expected to occur during the display of the first frame;

responsive to the start of the display of the first frame, driving the first sequence of PWM cycles on the PWM data signal by driving PWM cycles having the first predetermined duty ratio and incrementing a first count for each driven PWM cycle until an occurrence of one of;

the first count being equal to the first number of completeable PWM cycles;

or the display of the first frame terminating before the first count is equal to the first number of completeable PWM cycles;

responsive to the count being less than the first number of completeable PWM cycles at the start of the second frame, decreasing a second number of completeable PWM cycles expected to occur during the display of the second frame;

responsive to the start of the display of the second frame, driving the second sequence of PWM cycles on the PWM data signal by driving PWM cycles having the second predetermined duty ratio and incrementing a second count for each driven PWM cycle until the second count is equal to the second number of completeable PWM cycles; and

responsive to the second count being equal to the second number of completeable PWM cycles, driving the PWM data signal at the second level until detecting the start of the display of the third frame.

6. The method of claim 1, wherein generating the PWM data signal further comprises:

determining a first number of completeable PWM cycles expected to occur during a display of a third frame, the display of the third frame prior to the display of the first frame;

responsive to the start of the display of the third frame, driving PWM cycles having a second predetermined duty ratio and incrementing a first count for each completed PWM cycle until the start of the first frame, the first count being less than the first number of completeable PWM cycles at the start of the first frame;

responsive to the first count being less than the first number of completeable PWM cycles, decreasing a second number of completeable PWM cycles expected to occur during the display of the first frame;

responsive to the start of the display of the first frame, driving the first sequence of PWM cycles on the PWM data signal by driving PWM cycles having the first predetermined duty ratio and incrementing a second count for each completed PWM cycle of the first sequence until the second count is equal to the second number of completeable PWM cycles; and

responsive to the second count being equal to the second number of completeable PWM cycles, driving the PWM data signal at the second level until detecting the start of the display of the second frame.

7. The method of claim 1, wherein generating the PWM data signal comprises:

determining a number of completeable PWM cycles expected to occur during the display of the first frame;

responsive to the start of the display of the first frame, driving the first sequence of PWM cycles on the PWM data signal by driving PWM cycles having the first predetermined duty ratio and incrementing a count for each driven PWM cycle until the count is equal to the number of completeable PWM cycles; and

responsive to the count being equal to the number of completeable PWM cycles, driving the PWM data signal at the second level until detecting the start of the display of the second frame.

8. The method of claim 1, further comprising:

generating a clock signal;

determining a PWM frequency signal based on the clock signal and a frame timing reference representative of a timing of a series of frames of the video data, the PWM frequency signal representative of a timing of the PWM cycles of the first sequence synchronized to the display of the first frame; and

wherein driving the PWM cycles having the first predetermined duty ratio comprises driving the PWM cycles based on the PWM frequency signal.

9. The method of claim 8, further comprising:

determining a PWM duty resolution signal based on the clock signal and the frame timing reference, the PWM duty resolution signal representative of a timing of PWM resolution steps of the PWM cycles of the first sequence synchronized to the display of the first frame; and

wherein driving the PWM cycles having the first predetermined duty ratio comprises driving the PWM cycles based on the PWM duty resolution signal.

10. In a display device comprising a light emitting diode (LED) driver configured to control one or more LEDs of the display device based on a pulse width modulation (PWM) data signal, a method comprising:

determining a frame timing reference associated with a display of a series of frames of video data at the display device;

driving, for a first frame of the series of one or more frames, a first sequence of pulse width modulation (PWM) cycles on the PWM data signal, the first sequence synchronized to a start of the first frame based on the frame timing reference and the first sequence comprising a first predetermined number of PWM cycles, wherein the PWM data signal transitions from a first level to a second level during each PWM cycle;

driving, for the first frame, the PWM data signal at the second level for a first duration responsive to determining the first predetermined number of PWM cycles have been driven for the first frame, the first duration different than the duration of a PWM cycle of the first sequence of PWM cycles;

terminating driving the PWM data signal at the second level responsive to a start of a second frame of the series of frames, the second frame following the first frame in the series; and

driving, for the second frame, a second sequence of PWM cycles on the PWM data signal, the second sequence synchronized to a start of the second frame based on the frame timing reference and the second sequence comprising a second predetermined number of PWM cycles.

11. The method of claim 10, further comprising:

driving, for the second frame, the PWM data signal at the second level responsive to determining the second predetermined number of PWM cycles have been driven for the second frame; and

terminating driving the PWM data signal at the second level responsive to a start of a third frame of the series of frames, the third frame following the second frame in the series.

12. The method of claim 11, wherein the first predetermined number of PWM cycles and the second predetermined number of PWM cycles comprise the same number of PWM cycles.

13. The method of claim 11, further comprising:

increasing the first predetermined number of PWM cycles to generate the second predetermined number of PWM cycles responsive to determining the PWM data signal was driven at the second level for the first frame for a duration greater than the duration of a PWM cycle of the second sequence.

14. The method of claim 11, further comprising:

generating a PWM frequency signal from a clock signal and the frame timing reference, the PWM frequency signal representative of a timing of the PWM cycles of the first sequence synchronized to the display of the first frame; and

determining the duration of each PWM cycle of the second sequence based on the PWM frequency signal.

15. A system comprising:

a pulse width modulation (PWM) generation module comprising an output configured to be coupled to a light emitting diode (LED) driver of a display device, the PWM generation module configured to generate a PWM data signal for output to the LED driver, the PWM data signal comprising;

a first sequence of PWM cycles having a first predetermined duty ratio, an initial PWM cycle of the first sequence being synchronized to a start of a display of a first frame of a video data. wherein the PWM data signal transitions from a first level to a second level during each PWM cycle;

a first portion of the PWM data signal starting in the first frame following the first sequence of PWM cycles and terminating responsive to a start of a display of a second frame of the video data at the display device, the second frame following the first frame, the first portion having a level matching the second level for the duration of the first portion, the duration of the first portion different than the duration of a PWM cycle of the first sequence of PWM cycles; and

a second sequence of PWM cycles, an initial PWM cycle of the second sequence being synchronized to the start of the second frame.

16. The system of claim 15, the PWM generation module further is configured to generate the PWM data signal as further comprising:

a second portion of the PWM data signal starting in the second frame following the second sequence of PWM cycles and terminating responsive to a start of a display of a third frame following the second frame, the second portion having a level matching the second level for the duration of the second portion, the duration of the second portion different than the duration of a PWM cycle of the second sequence of PWM cycles, the second sequence of PWM cycles having a second predetermined duty ratio.

17. The system of claim 16, wherein the PWM generation module further is configured to:

increase a number of PWM cycles to be implemented in the second sequence of PWM cycles responsive to determining the duration of the first portion is greater than the duration of the PWM cycle of the first sequence.

18. The system of claim 15, wherein the PWM generation module comprises:

a counter comprising an input to receive a clock signal and an output to provide a first signal representative of a number of oscillations of the clock signal per frame of the video data;

a frequency synthesizer configured to generate a second signal and a third signal based on the first signal, a first indicator representative of an expected number of completeable PWM cycles per frame of the video data, and a second indicator representative of a duty resolution of the PWM cycles in the first sequence, the second signal representative of a timing of the PWM cycles of the first sequence synchronized to the display of the first frame, and the third signal representative of a timing of PWM resolution steps of the PWM cycles of the first sequence synchronized to the display of the first frame.

19. The system of claim 18, wherein the PWM generation module further comprises:

a PWM signal generator configured to generate the PWM data signal based on the second signal, the third signal, a third indicator representative of a duty ratio of the PWM cycles of the first sequence, and a frame signal representative of a timing of frames of the video data.

20. The system of claim 15, further comprising:

the LED driver; and

the display device.