Ferroelectric memory device and method with reference potential correction capacitor(s)

• US 8,374,017 B2
• Filed: 09/14/2009
• Issued: 02/12/2013
• Est. Priority Date: 10/24/2008
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takizawa, Ryousuke, Takashima, Daisaburo
• Primary Examiner(s): Nguyen, Tuan T
• Assistant Examiner(s): REIDLINGER, RONALD LANCE
• Application Number:
  US12/559,447
• Publication Number:
  US 20100103715A1
• Time in Patent Office: 1,247 Days
• Field of Search: 365/145, 365/210.11
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

A semiconductor storage device includes: a plurality of memory cell arrays, each having a memory cell arranged therein, the memory cell including a ferroelectric capacitor and a transistor; a dummy capacitor operative to provide a reference potential corresponding to a potential read from the memory cell; a sense amplifier circuit including an amplifier circuit to compare and amplify potentials between a pair of bit lines; a reference potential correction capacitor connected to the pair of bit lines together with the dummy capacitor; and a control circuit configured to output a correction signal based on shift information to correct the reference potential, the shift information being retained in at least one of the plurality of memory cell arrays. The reference potential correction capacitor shifts the reference potential by changing the amount of accumulated electric charges according to the correction signal.

Claims

1. A semiconductor storage device comprising:

a plurality of arrays of memory cells, each memory cell including a ferroelectric capacitor and a transistor, the plurality of memory cell arrays comprising;

word lines operative to select memory cells in the array,

plate lines operative to apply drive voltage to the ferroelectric capacitors in the array, and

a pair of bit lines operative to read data from the ferroelectric capacitors in the array;

a selection transistor operative to selectively connect a memory cell block to one bit line of the pair of bit lines;

a dummy capacitor operative to provide a reference voltage to another bit line of the pair of bit lines, the reference voltage having a value between signals that may be read from the memory cell;

a sense amplifier circuit to compare and amplify potentials between the bit lines of the pair of bit lines;

a reference potential correction capacitor connected to the pair of bit lines together with the dummy capacitor; and

a control circuit configured to output a correction signal based on shift information to correct the reference potential, the shift information being retained in at least one of the plurality of memory cell arrays,

the reference potential correction capacitor shifting the reference potential by changing the amount of accumulated electric charges according to the correction signal.

2. The device of claim 1, wherein

the control circuit is configured to output different correction signals based on the shift information to the reference potential correction capacitor depending on the word line to be selected.

3. The device of claim 2, wherein

the shift information is read from a first memory cell in the memory cell arrays that stores the shift information, the first memory cell being connected to the same word line as a second memory cell from which data is read.

4. The device of claim 1, further comprising:

a plurality of cell array mats each including a certain number of the memory cell arrays; and

a plurality of latch circuits, each of which is provided for each of the cell array mats to retain the shift information,

wherein the control circuit is configured to output a different correction signal to the reference potential correction capacitor for each of the cell array mats, based on the shift information transferred from each of the latch circuits.

5. The device of claim 4, wherein

each of the latch circuits is configured to retain the shift information read from one of the memory cell arrays when the semiconductor storage device is powered on.

6. The device of claim 4, wherein

the shift information is stored in a shift information storage area provided for each of the cell array mats.

7. The device of claim 1, further comprising a plurality of latch circuits, each latch circuit being provided for each of the pair of bit lines to retain the shift information,

wherein at least one reference potential correction capacitor is provided for each of the pair of bit lines, and the control circuit is configured to output a different correction signal to the at least one reference potential correction capacitor for each of the bit lines, based on the shift information transferred from each of the latch circuits.

8. The device of claim 1, wherein

the memory cell is formed with the ferroelectric capacitor and the transistor connected in parallel, and

the memory cell block has a plurality of the memory cells connected in series with one end connected to the plate line and the other end connected to the pair of bit lines via the selection transistor.

9. The device of claim 1, wherein

a plurality of the reference potential correction capacitors are provided at one bit line of the pair of bit lines.

10. The device of claim 9, wherein

different correction signals are input to different reference potential correction capacitors.

11. A method of operating a semiconductor storage device, the method comprising:

reading data from a ferroelectric capacitor of a memory cell to one bit line of a pair of bit lines, the memory cell including the ferroelectric capacitor and a transistor and being arranged in each of a plurality of memory cell arrays;

providing, by a dummy capacitor, a reference voltage to another bit line of the pair of bit lines, the reference voltage having a value between signals that may be read from the memory cell;

outputting, by a control circuit, a correction signal based on shift information to correct a reference potential, the shift information being retained in at least one of the plurality of memory cell arrays;

shifting, by a reference potential correction capacitor connected to the pair of bit lines, the reference potential by changing the amount of accumulated electric charges of the correction signal; and

comparing and amplifying, by a sense amplifier circuit, potentials between the pair of bit lines.

12. The method of claim 11, wherein

shifting the reference potential comprises shifting, by the reference potential correction capacitor, the reference potential to a different value depending on the word line to be selected.

13. The method of claim 11, wherein

the semiconductor storage device further comprises a plurality of cell array mats each including a certain number of the memory cell arrays;

and

shifting the reference potential comprises shifting, by the reference potential correction capacitor, the reference potential to a different value for each of the cell array mats.

14. The method of claim 11, wherein

shifting the reference potential comprises shifting, by the reference potential correction capacitor provided for each of the pair of bit lines, the reference potential to a different value for each of the bit lines.

15. The method of claim 11, wherein

shifting the reference potential is performed by a plurality of the reference potential correction capacitors provided for one bit line of the pair of bit lines.