DES hardware throughput for short operations

• US 8,374,343 B2
• Filed: 04/18/2008
• Issued: 02/12/2013
• Est. Priority Date: 05/01/2000
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lindemann, Mark, Perez, Ronald, Smith, Sean William
• Primary Examiner(s): Zand, Kambiz
• Assistant Examiner(s): Tran, Tongoc
• Application Number:
  US12/106,013
• Publication Number:
  US 20080192926A1
• Time in Patent Office: 1,761 Days
• Field of Search: 380/259, 380 28- 30, 380/44, 380/47, 380/33
• US Class Current: 380/29
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 9/0625 with splitting of the data block into left and right halves, e.g. Feistel based algorithms, DES, FEAL, IDEA or KASUMI

Abstract

A system for executing a symmetric key cryptographic method includes a processor selecting data paths, a key, an initialization vector, a memory storing batched operation parameters, a bus connected to the processor and the memory, a cryptographic processor connected to the bus and controlled by the processor for performing a plurality of operations according to the operations parameter, wherein data for each operation is received individually and separately from the batched operation parameters, wherein an output for each operation is transmitted separately, and a pair of first-in-first-out (FIFO) state machines controlled by the processor and selectably connected to one of the cryptographic processor and the bus, bypassing the cryptographic processor.

Claims

1. A system for executing a symmetric key cryptographic method comprising:

a processor selecting data paths, a key, an initialization vector;

a memory storing batched operation parameters;

a bus connected to the processor and the memory;

a cryptographic processor connected to the bus and controlled by the processor for performing a plurality of operations according to the operations parameter, wherein data for each operation is received individually and separately from the batched operation parameters, wherein an output for each operation is transmitted separately; and

a pair of first-in-first-out (FIFO) state machines controlled by the processor and selectably connected to the processor via the cryptographic processor or the bus, wherein the bus bypasses the cryptographic processor.

2. The system of claim 1, further comprising a pair of controllers connected to the bus for controlling input and output of the operations to and from the memory via the bus, wherein the pair of controllers operate without control of the processor.

3. The system of claim 1, further comprising the pair of first-in-first-out (FIFO) state machines selected to be connected to the cryptographic processor for transmitting the data for each operation to the cryptographic processor individually and separately from the batch for an external-to-external cryptographic operation.

8. The system of claim 2, wherein each of the controllers are connected between a respective one of the pair of first-in-first-out (FIFO) state machines and the bus.

4. A system for executing a symmetric key cryptographic method comprising:

a processor selecting data paths, a key, an initialization vector;

a memory storing batched operation parameters, wherein the memory does not store data of for operations corresponding to the operation parameters;

a bus connected to the processor and the memory;

a cryptographic processor connected to the bus and controlled by the processor for performing a plurality of operations according to the operations parameter, wherein data for each operation is received individually and separately from the batched operation parameters; and

a pair of first-in-first-out (FIFO) state machines controlled by the processor and selectably connected to the processor via the cryptographic processor or the bus, wherein the bus bypasses the cryptographic processor.

5. The system of claim 4, further comprising a pair of controllers connected to the bus for controlling input and output of the operations to and from the memory via the bus, wherein the pair of controllers operate without control of the processor.

6. The system of claim 4, further comprising the pair of first-in-first-out (FIFO) state machines selected to be connected to the cryptographic processor for transmitting the data for each operation to the cryptographic processor individually and separately from the batch for an external-to-external cryptographic operation.

7. The system of claim 4, wherein an output for each operation is transmitted separately.

9. The system of claim 5, wherein each of the controllers are connected between a respective one of the pair of first-in-first-out (FIFO) state machines and the bus.