Semiconductor storage device

• US 8,378,425 B2
• Filed: 02/03/2010
• Issued: 02/19/2013
• Est. Priority Date: 01/29/2008
• Status: Active Grant

• Current Assignee: Unisantis Electronics Singapore Pte. Ltd. (NewScope Group Holdings AG)
• Original Assignee: Unisantis Electronics Singapore Pte. Ltd. (NewScope Group Holdings AG)
• Inventors: Masuoka, Fujio, Arai, Shintaro
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): CHIU, TSZ K
• Application Number:
  US12/699,647
• Publication Number:
  US 20100219483A1
• Time in Patent Office: 1,112 Days
• Field of Search: 257/368, 257/379, 257/393, 257/E21.661, 257/E21.703, 257/E27.099, 257/E27.112, 438/238, 438/275, 438/279
• US Class Current: 257/368
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

It is intended to achieve a sufficiently-small SRAM cell area and a stable operation margin in a CMOS 6T-SRAM comprising a vertical transistor SGT. In a static type memory cell made up using six MOS transistors, each of the MOS transistor constituting the memory cell is formed on a planar silicon layer formed on a buried oxide film, to have a structure where a drain, a gate and a source are arranged in a vertical direction, wherein the gate is formed to surround a pillar-shaped semiconductor layer. The planar silicon layer comprises a first active region having a first conductive type, and a second active region having a second conductive type. The first and second active regions are connected to each other through a silicide layer formed in a surface of the planar silicon layer to achieve an SRAM cell having a sufficiently-small area.

Claims

1. A semiconductor storage device comprising a static type memory cell in which six MOS transistors are arrayed on a dielectric film formed on a substrate, wherein:

each of the six MOS transistors serves as (a) first and second NMOS access transistors each operable to access to the memory cell, (b) first and second NMOS driver transistors each operable to drive a storage node to hold data in the memory cell, and (c) first and second PMOS load transistors each operable to supply electric charges to hold data in the memory cell,

each of the first and second NMOS access transistors comprises a first diffusion layer, which is layered, along with a first pillar-shaped semiconductor layer and a second diffusion layer, vertically on the dielectric film formed on the substrate, the first pillar-shaped semiconductor layer being disposed between the first and second diffusion layers, and the first pillar-shaped semiconductor layer being formed with a gate arranged along a sidewall thereof,

each of the first and second NMOS driver transistors comprises a third diffusion layer, which is layered, along with a second pillar-shaped semiconductor layer and a fourth diffusion layer, vertically on the dielectric film formed on the substrate, the second pillar-shaped semiconductor layer being disposed between the third and fourth diffusion layers, the second pillar-shaped semiconductor layer being formed with a gate arranged along a sidewall thereof, and

each of the first and second PMOS load transistors comprises a fifth diffusion layer, which is layered, along with a third pillar-shaped semiconductor layer and a sixth diffusion layer, vertically on the dielectric film formed on the substrate, the third pillar-shaped semiconductor layer being disposed between the fifth and sixth diffusion layers, the third pillar-shaped semiconductor layer being formed with a gate arranged along a sidewall thereof, and further wherein;

the first NMOS access transistor, the first NMOS driver transistor and the first PMOS load transistor are arrayed adjacent to each other;

the second NMOS access transistor, the second NMOS driver transistor and the second PMOS load transistor are arrayed adjacent to each other;

the first diffusion layer of the first NMOS access transistor, the third diffusion layer of the first NMOS driver transistor and the fifth diffusion layer of the first PMOS load transistor are arranged on the dielectric film to serve as a first storage node for holding data therein;

the first diffusion layer, the third diffusion layer and the fifth diffusion layer are connected to each other through a first silicide layer formed on respective surfaces of the first, third and fifth diffusion layers;

the first diffusion layer of the second NMOS access transistor, the third diffusion layer of the second NMOS driver transistor and the fifth diffusion layer of the second PMOS load transistor are arranged on the dielectric film to serve as a second storage node for holding data therein; and

the first diffusion layer, the third diffusion layer and the fifth diffusion layer are connected to each other through a second silicide layer formed on respective surfaces of the first, third and fifth diffusion layers serving as the second storage node.

2. The semiconductor storage device as defined in claim 1, wherein:

the gates of the first NMOS driver transistor and the first PMOS load transistor formed on the diffusion layers to serve as the first storage node are each formed with a first gate line extending therefrom which is connected to a first common contact; and

the gates of the second NMOS driver transistor and the second PMOS load transistor formed on the diffusion layers to serve as the second storage node are each formed with a second gate line extending therefrom which is connected to a second common contact.

3. The semiconductor storage device as defined in claim 1, wherein the sidewall of each of the pillar-shaped semiconductor layers forming the first and second NMOS driver transistors is longer in peripheral length than the sidewall of each of the pillar-shaped semiconductor layers forming the first and second PMOS road transistors.

4. The semiconductor storage device as defined in claim 1, wherein the pillar-shaped semiconductor layers forming the first and second NMOS driver transistors are oval in cross-section, and the sidewall of each of the pillar-shaped semiconductor layers forming the first and second NMOS driver transistors is thereby made longer in peripheral length than the sidewall of each of the pillar-shaped semiconductor layers forming the first and second PMOS road transistors.

5. The semiconductor storage device as defined in claim 1, wherein the sidewall of each of the pillar-shaped semiconductor layers forming the first and second NMOS driver transistors is longer in peripheral length than the sidewall of each of the pillar-shaped semiconductor layers forming the first and second NMOS access transistors.

6. The semiconductor storage device as defined in claim 1, wherein the pillar-shaped semiconductor layers forming the first and second NMOS driver transistors are oval in cross-section, and the sidewall of each of the pillar-shaped semiconductor layers forming the first and second NMOS driver transistors is thereby made longer in peripheral length than the sidewall in each of the pillar-shaped semiconductor layers forming the first and second NMOS access transistors.

7. The semiconductor storage device as defined in claim 1, wherein the sidewall of each of the pillar-shaped semiconductor layers forming the first and second PMOS road transistors is shorter in peripheral length than the sidewall of each of the pillar-shaped semiconductor layers forming the first and second NMOS access transistors.

8. The semiconductor storage device as defined in claim 1, wherein at least one of third and fourth contacts formed on third and fourth gate lines extending respectively from gate electrodes of the first and second NMOS access transistors provides a common contact formed on a gate line extending from a gate electrode of an NMOS access transistor in an adjacent memory cell.

9. The semiconductor storage device as defined in claim 1, wherein the pillar-shaped semiconductor layers are arrayed in a hexagonal lattice pattern.

10. The semiconductor storage device as defined in claim 1, wherein:

the gates of the first NMOS driver transistor and the first PMOS load transistor formed on the diffusion layers to serve as the first storage node are each formed with a fifth gate line extending therefrom which is connected to one of the diffusion layers serving as the second storage node, through a first common contact; and

the gates of the second NMOS driver transistor and the second PMOS load transistor formed on the diffusion layers to serve as the second storage node are each formed with a sixth gate line extending therefrom which is connected to one of the diffusion layers serving as the first storage node, through a second common contact.

11. The semiconductor storage device as defined in claim 1, wherein the six MOS transistors are arranged on the dielectric film in an array of three rows by two columns, wherein:

the first NMOS access transistor is arranged at an intersection of the 1st row and the 1st column;

the first PMOS load transistor is arranged at an intersection of the 2nd row and the 1st column;

the first NMOS driver transistor is arranged at an intersection of the 3rd row and the 1st column;

the second NMOS access transistor is arranged at an intersection of the 3rd row and the 2nd column;

the second PMOS load transistor is arranged at an intersection of the 2nd row and the 2nd column; and

the second NMOS driver transistor is arranged at an intersection of the 1st row and the 2nd column.

12. The semiconductor storage device as defined in claim 1, wherein the six MOS transistors are arranged on the dielectric film in an array of three rows by two columns, wherein:

the first NMOS access transistor is arranged at an intersection of the 1st row and the 1st column;

the first PMOS load transistor is arranged at an intersection of the 3rd row and the 1st column;

the first NMOS driver transistor is arranged at an intersection of the 2nd row and the 1st column;

the second NMOS access transistor is arranged at an intersection of the 3rd row and the 2nd column;

the second PMOS load transistor is arranged at an intersection of the 1st row and the 2nd column; and

the second NMOS driver transistor is arranged at an intersection of the 2nd row and the 2nd column.

13. The semiconductor storage device as defined in claim 1, wherein the six MOS transistors are arranged on the dielectric film in an array of three rows by two columns, wherein:

the first NMOS access transistor is arranged at an intersection of the 1st row and the 1st column;

the first PMOS load transistor is arranged at an intersection of the 3rd row and the 1st column;

the first NMOS driver transistor is arranged at an intersection of the 2nd row and the 1st column;

the second NMOS access transistor is arranged at an intersection of the 1st row and the 2nd column;

the second PMOS load transistor is arranged at an intersection of the 3rd row and the 2nd column; and

the second NMOS driver transistor is arranged at an intersection of the 2nd row and the 2nd column.

14. The semiconductor storage device as defined in claim 13, wherein a fifth contact formed on a seventh gate line extending from the gate of the first NMOS access transistor provides a common contact formed on a gate line extending from the gate of the second NMOS access transistor.

15. The semiconductor storage device as defined in claim 1, wherein the six MOS transistors are arranged on the dielectric film in an array of two rows by three columns, wherein:

the first NMOS access transistor is arranged at an intersection of the 1st row and the 1st column;

the first PMOS load transistor is arranged at an intersection of the 2nd row and the 2nd column;

the first NMOS driver transistor is arranged at an intersection of the 2nd row and the 1st column;

the second NMOS access transistor is arranged at an intersection of the 2nd row and the 3rd column;

the second PMOS load transistor is arranged at an intersection of the 1st row and the 2nd column; and

the second NMOS driver transistor is arranged at an intersection of the 1st row and the 3rd column.