Adaptable datapath for a digital processing system

• US 8,380,884 B2
• Filed: 03/07/2011
• Issued: 02/19/2013
• Est. Priority Date: 10/28/2002
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Ramchandran, Amit
• Primary Examiner(s): Lee, Chun-Kuan
• Assistant Examiner(s): LEWIS-TAYLOR, DAYTON A.
• Application Number:
  US13/042,391
• Publication Number:
  US 20110161535A1
• Time in Patent Office: 715 Days
• Field of Search: None
• US Class Current: 710/4
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/287 Multiplexed DMA G06F13/30 takes precedence
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention includes an adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., Discrete Cosine Transform (DCT), Fast-Fourier Transform (FFT) and other operations. Other features are provided.

Claims

1. A reconfigurable data path circuit coupled to a memory bus for obtaining data from a memory, the reconfigurable data path circuit comprising:

a plurality of functional units configured to perform a digital operation;

one or more data address generators coupled to the memory bus;

a configurable data path configurably coupled to the one or more data address generators and the plurality of functional units, the configurable data path being configurable in response to a first configuration information by configuring or reconfiguring at least one interconnection between the one or more data address generators and the plurality of functional units;

wherein the one or more data address generators are coupled to the memory bus and the configurable data path, each of the one or more data address generators being configurable in response to a second configuration information that is different from the first configuration information to generate memory addresses from which data is to be read from or written to the memory for the data path configuration; and

wherein the second configuration information includes predication information, the generation of the memory addresses in response to the second configuration information being conditioned upon the predication information.

2. A reconfigurable data path circuit of claim 1, wherein each of the one or more data address generators is configurable as a function of both the predication information and other information in the second configuration information to determine whether to generate one of the memory addresses in response to the second configuration information.

3. The reconfigurable data path circuit of claim 2, wherein each of the one or more data address generators is configurable as a function of the predication information to operate other than generating one of the memory addresses.

4. The reconfigurable data path circuit of claim 1, wherein each of the one or more data address generators is configurable for non-sequential operation as a function of the predication information.

5. The reconfigurable data path circuit of claim 1, wherein the first and second configuration information each comprises a separate control word.

6. The reconfigurable data path circuit of claim 5, wherein each separate control word includes an operation field including the predication information.

7. The reconfigurable data path circuit of claim 6, wherein each separate control word further comprises an address field designating one of the memory addresses.

8. The reconfigurable data path circuit of claim 1, wherein the one or more data address generators are further configurable or reconfigurable in response to the second configuration information to read data of one or more widths from the memory bus consistent with and for the data path configuration.

9. The reconfigurable data path circuit of claim 1, wherein the one or more data address generators are configurable in response to the second configuration information to split data received from the memory bus onto the configurable data path.

10. The reconfigurable data path circuit of claim 9, wherein the one or more data address generators transfer data to the configurable data path for processing by the functional units in parallel.

11. The reconfigurable data path circuit of claim 1, wherein the configurable data path is reconfigurable to change from a first data path configuration having one 16 bit path to a second data path configuration having two 8 bit paths in response to the first configuration information;

and each of the one or more data address generators is configurable in response to the second configuration information to generate two memory addresses for writing and reading two 8 bit words for the second data path configuration, and wherein the generation of the two memory addresses is conditioned upon the predication information.

12. The reconfigurable data path circuit of claim 1, wherein the one or more data address generators are further configurable in response to the second configuration information for transferring data to the memory bus for writing to the memory, the generation of a respective memory address for the writing of the data being conditioned upon the predication information.

13. The reconfigurable data path circuit of claim 1, wherein the plurality of functional units include a multiplier and an accumulator, the accumulator being adapted to accumulate outputs from the multipliers into a register, the reconfigurable data path circuit further comprising a direct data path coupling the multiplier and the accumulator.

14. The reconfigurable data path circuit of claim 13, wherein the plurality of functional units further includes an Arithmetic Logic Unit (ALU).

15. The reconfigurable data path circuit of claim 1, further comprising a plurality of register files each configurably interconnected by the configurable data path to the plurality of functional units and to one of the one or more data address generators.

16. The reconfigurable data path circuit of claim 1, wherein the configurable data path further comprises a reconfigurable interconnection network configurable for configuring or reconfiguring the interconnections between the one or more data address generators and the plurality of functional units for the data path configuration.

17. The reconfigurable data path circuit of claim 16, wherein the reconfigurable interconnection network includes a plurality of groups of data lines configurably coupled to the one or more data address generators and the plurality of functional units.

18. The reconfigurable data path circuit of claim 17, wherein the reconfigurable interconnection network is configurable or reconfigurable to create portions of the reconfigurable data path having different widths, the portions being coupled between the one or more data address generators and the plurality of functional units.

19. The reconfigurable data path circuit of claim 15, wherein the configurable data path further comprises a reconfigurable interconnection network comprising a plurality of groups of data lines configurably coupled to the one or more data address generators, the functional units, and the plurality of register files in the configurable data path, wherein each register file of the plurality of register files is coupled to a group of data lines of the plurality of groups of data lines in the configurable data path in a one-to-one correspondence, the plurality of register files being adapted for storing data from the respective group of data lines to which the respective ones of the plurality of register files is coupled.

20. The reconfigurable data path circuit of claim 1, wherein the interconnections between the configurable data path and the one or more data address generators are configurable in real time.

21. The reconfigurable data path circuit of claim 1, wherein at least one of the plurality of functional units is configurable to provide at least two different functions.

22. The reconfigurable data path circuit of claim 16, wherein the plurality of functional units are configurable to provide a second plurality of configurable data paths between respective ones of the plurality of functional units and the reconfigurable interconnection network.

23. The reconfigurable data path circuit of claim 22, wherein the second plurality of configurable data paths are configurable for a plurality of data widths.

24. The reconfigurable data path circuit of claim 1, wherein each of the functional units of the plurality of functional units comprises one of a multiplier, an accumulator, a data cache, an Arithmetic Logic Unit (ALU), or a register file.

25. The reconfigurable data path circuit of claim 24, wherein the reconfigurable data path includes the multiplier, the accumulator, the data cache, the Arithmetic Logic Unit (ALU), the register file, and the reconfigurable data path includes interconnects between the functional units of the reconfigurable data path.

26. The reconfigurable data path circuit of claim 1, wherein each of the one or more data address generators is further configurable in response to the second configuration information to control memory addresses from which data is to be read from or written to the memory for the data path configuration, the control of the memory addresses in response to the second configuration information being conditioned upon the predication information.

27. A digital processing system comprising:

a memory bus coupled to a memory; and

a reconfigurable data path circuit coupled to the memory bus for obtaining data from the memory, the reconfigurable data path circuit comprising;

a plurality of functional units configurable to perform a digital operation; and

one or more data address generators coupled to the memory bus;

a configurable data path configurably coupled to the one or more data address generators and the plurality of functional units, the configurable data path being configurable in response to a first configuration information by configuring or reconfiguring at least one interconnection between the one or more data address generators and the plurality of functional units;

wherein the one or more data address generators are coupled to the memory bus and the configurable data path, each of the one or more data address generators being configurable in response to a second configuration information that is different from the first configuration information to generate memory addresses from which data is to be read from or written to the memory for the data path configuration; and

wherein the second configuration information includes predication information, the generation of the memory addresses in response to the second configuration information being conditioned upon the predication information.

28. The digital processing system of claim 27, wherein each of the one or more data address generators is further configurable in response to the second configuration information to control memory addresses from which data is to be read from or written to the memory for the data path configuration, the control of the memory addresses in response to the second configuration information being conditioned upon the predication information.

29. The digital processing system of claim 27, wherein each of the one or more data address generators is configurable as a function of both the predication information and other information in the second configuration information to determine whether to generate one of the memory addresses in response to the second configuration information.

30. The digital processing system of claim 27, wherein the configurable data path further comprises a reconfigurable interconnection network comprising the plurality of groups of data lines and being configurable for configuring or reconfiguring the interconnections between or among the one or more data address generators and the plurality of functional units for the data path configuration.

31. The digital processing system of claim 30, wherein the reconfigurable interconnection network is configurable or reconfigurable to create portions of the reconfigurable data paths having different widths, the portions being coupled between the one or more data address generators and the plurality of functional units.

32. The digital processing system of claim 30, wherein the plurality of functional units include a multiplier, an accumulator, and an Arithmetic Logic Unit (ALU), the reconfigurable data path circuit further comprising a direct data path coupling the multiplier and the accumulator.

33. The digital processing system of claim 27, wherein at least one of the plurality of functional units is configurable to provide two different functions.