On-off keying using vector modulation

• US 8,385,461 B1
• Filed: 04/20/2010
• Issued: 02/26/2013
• Est. Priority Date: 04/20/2009
• Status: Active Grant

• Current Assignee: Vubiq Networks, Inc.
• Original Assignee: Vubiq, Inc.
• Inventors: Pettus, Michael Gregory, Nadeau, Larry Bruce
• Primary Examiner(s): Corrielus, Jean B
• Application Number:
  US12/764,084
• Time in Patent Office: 1,043 Days
• Field of Search: 375/259, 375/295, 375/261, 375/268, 375/298, 375/283, 375/300, 375/318, 375/244, 375237-239, 332/103, 332/149, 332/109, 332/112, 332/115, 370212-213
• US Class Current: 375/295
• CPC Class Codes: H04L 27/04 Modulator circuits; Transmitter circuits

Abstract

A system and method including deriving a subcarrier frequency from a binary data stream having a clock frequency, wherein the subcarrier frequency is substantially the same as the clock frequency; gating the subcarrier frequency using the data stream to produce a modulated OOK signal; determining a OOK subcarrier center frequency based on the modulated OOK signal with the clock frequency; delaying the modulated OOK signal relative to the binary data stream by a predetermined amount to produce a delayed modulated OOK signal; conditioning the modulated OOK signal and the delayed modulated OOK signal to create a differential transition signal in an I channel and a Q channel to provide a stable amplitude signal level reference at an input to an I and Q vector modulator.

Claims

1. A method comprising:

deriving a subcarrier frequency from a binary data stream having a clock frequency, wherein the subcarrier frequency is substantially the same as the clock frequency;

gating the subcarrier frequency using the data stream to produce a modulated on-off keying signal;

delaying the modulated on-off keying signal relative to the binary data stream by a predetermined amount to produce a delayed modulated on-off keying signal; and

conditioning the modulated on-off keying signal and the delayed modulated on-off keying signal to create a differential transition signal in an in-phase channel and a quadrature-phase channel to provide a stable amplitude signal level reference at an input to an in-phase and quadrature-phase vector modulator.

2. A device comprising:

means for deriving a subcarrier frequency from a binary data stream having a clock frequency, wherein the subcarrier frequency is substantially the same as the clock frequency;

means for gating the subcarrier frequency using the data stream to produce a modulated on-off keying signal;

means for delaying the modulated on-off keying signal relative to the binary data stream by a predetermined amount to produce a delayed modulated on-off keying signal; and

means for conditioning the modulated on-off keying signal and the delayed modulated on-off keying signal to create a differential transition signal in an in-phase channel and a quadrature-phase channel to provide a stable amplitude signal level reference at an input to an in-phase and quadrature-phase vector modulator.

3. A method comprising:

separating a binary data stream into a clock signal and a data signal;

producing a plurality of clock signals and a plurality of data signals from the clock signal and the data signal;

gating the plurality of clock signals using the plurality of data signals to produce a plurality of on-off keying modulated signals;

delaying two or more of the plurality of on-off keying modulated signals to create a first set of on-off keying modulated signals and a second set of on-off keying modulated signals wherein the first set of on-off keying modulated signals has a 90 degree phase lag with respect to the second set of on-off keying modulated signals.

4. The method of claim 3 further comprising:

delaying at least of one of the data signal or the clock signal to optimize a phase relationship between the data signal and the clock signal prior to the step of gating.

5. The method of claim 3 wherein the gating step is performed using AND logic.

6. The method of claim 3 further comprising:

coupling the first set of on-off keying modulated signals to an in-phase input of a vector modulated transmitter; and

coupling the second set of on-off keying modulated signals to a quadrature-phase input of the vector modulated transmitted.

7. A device comprising:

means for separating a binary data stream into a clock signal and a data signal;

means for producing a plurality of clock signals and a plurality of data signals from the clock signal and the data signal;

means for gating the plurality of clock signals using the plurality of data signals to produce a plurality of on-off keying modulated signals; and

means for delaying two or more of the plurality of on-off keying modulated signals to create a first set of on-off keying modulated signals and a second set of on-off keying modulated signals wherein the first set of on-off keying modulated signals has a 90 degree phase lag with respect to the second set of on-off keying modulated signals.

8. The device of claim 7 further comprising:

means for delaying at least of one of the data signal or the clock signal to optimize a phase relationship between the data signal and the clock signal.

9. The device of claim 7 wherein the gating means utilizes AND logic.

10. The device of claim 7 further comprising:

means for coupling the first set of on-off keying modulated signals to an in-phase input of a vector modulated transmitter; and

means for coupling the second set of on-off keying modulated signals to a quadrature-phase input of the vector modulated transmitter.