Massively parallel interconnect fabric for complex semiconductor devices

• US 8,390,035 B2
• Filed: 05/06/2009
• Issued: 03/05/2013
• Est. Priority Date: 05/06/2009
• Status: Active Grant

• Current Assignee: Farhang Yazdani, Majid Bemanian
• Original Assignee: Farhang Yazdani, Majid Bemanian
• Inventors: Bemanian, Majid, Yazdani, Farhang
• Primary Examiner(s): Lee, Eugene
• Assistant Examiner(s): Jiang, Fang-Xing
• Application Number:
  US12/436,235
• Publication Number:
  US 20100283085A1
• Time in Patent Office: 1,399 Days
• Field of Search: 257/209, 257/777, 257/E29.302, 326/39, 326/38, 361/760, 438/108, 438/132, 345/530, 713/1
• US Class Current: 257/209
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01058 : Cerium [Ce]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF.

Claims

1. A semiconductor device with multiple die assembly comprising:

a programmable semiconductor die substrate; and

a context die substrate;

said programmable semiconductor die substrate comprises multiple logic blocks;

said context die substrate is flipped on said programmable semiconductor die substrate;

said multiple logic blocks of said programmable semiconductor die substrate are electrically connected at transistor level or logic gate level, with wirebondless and bumpless electrical connections, via said context die substrate, through pads of a multiple parallel interconnect fabric;

said context die substrate implements a custom application of said semiconductor device by using said multiple logic blocks via electrical connections through pads of said multiple parallel interconnect fabric to said multiple logic blocks;

a programming interface;

wherein said programming interface is located on opposite surface from flipped surface of said context die substrate, so that after connection, said context die substrate is programmed through said programming interface;

wherein said context die substrate comprises programmable switches that electrically connect pads on said context die substrate, causing electrical connection between gates and transistors, in logic blocks, on said programmable semiconductor die substrate;

wherein said programmable semiconductor die substrate comprises a platform fabric input-output;

wherein said platform fabric input-output provides input and output for specific purpose function of serializer and deserializer functional blocks, to convert data between serial data and parallel interfaces in each direction for communications;

said programming interface feeds into a first memory which drives said programmable switches and controlled selectors.

2. The semiconductor device with multiple die assembly as recited in claim 1, wherein a first set of pads of said pads of said multiple interconnect fabric on said programmable semiconductor die substrate is electrically connected to a first component of said programmable semiconductor, said first component providing a first base core functionality;

a second set of pads of said pads of said multiple interconnect fabric on said programmable semiconductor die substrate is electrically connected to a second component of said programmable semiconductor, said second component providing a second base core functionality; and

said context die substrate provides said custom application using said first base core functionality and said second base core functionality by electrically connecting one or more pads of said first set of pads to one or more pads of said second set of pads through one or more of said pads of said multiple parallel interconnect fabric.

3. The semiconductor device with multiple die assembly as recited in claim 1, wherein said multiple parallel interconnect fabric has at least 4000 pad-to-pad connections.

4. The semiconductor device with multiple die assembly as recited in claim 1, wherein said multiple parallel interconnect fabric has a range of 10,000-100,000,000 pad-to-pad connections.

5. The semiconductor device with multiple die assembly as recited in claim 1, wherein said multiple parallel interconnect fabric comprises pads, metal layers, vias, and redistribution layers.

6. The semiconductor device with multiple die assembly as recited in claim 1, wherein said programmable semiconductor flipped into a package substrate, to provide electrical connection between said programmable semiconductor die substrate and said package substrate.

7. The semiconductor device with multiple die assembly as recited in claim 1, wherein each of said multiple logic blocks comprises one or more logic elements.

8. The semiconductor device with multiple die assembly as recited in claim 7, wherein said one or more logic elements comprise combinational logic or lookup table.

9. The semiconductor device with multiple die assembly as recited in claim 7, wherein said one or more logic elements comprise a clocked flip-flop.