Integrating a first contact structure in a gate last process

• US 8,394,692 B2
• Filed: 11/01/2011
• Issued: 03/12/2013
• Est. Priority Date: 08/26/2008
• Status: Active Grant

• Current Assignee: Advanced Manufacturing Innovations Incorporated
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yeh, Chiung-Han, Wu, Ming-Yuan, Thei, Kong-Beng, Chuang, Harry, Liang, Mong-Song
• Primary Examiner(s): Pham, Hoai V
• Application Number:
  US13/286,276
• Publication Number:
  US 20120045889A1
• Time in Patent Office: 497 Days
• Field of Search: 438/197, 438/199, 438/523, 438/573, 438/575, 257/E21.632
• US Class Current: 438/199
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/66606 with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology H01L29/66621 takes precedence

Abstract

A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact.

Claims

1. A method comprising:

providing a semiconductor substrate;

forming a transistor that includes a gate structure disposed over the semiconductor substrate, a source feature, and a drain feature, wherein the gate structure interposes the source feature and the drain feature and the gate structure includes a dummy gate;

forming a first dielectric layer over the semiconductor substrate and the transistor;

forming a first contact feature having a first width in the first dielectric layer, wherein the first contact feature is coupled to one of the source feature and the drain feature;

removing a portion of the first dielectric layer such that the dummy gate of the gate structure is exposed and a portion of the first dielectric layer remains;

replacing the dummy gate of the gate structure with a metal gate;

after replacing the dummy gate, forming a second dielectric layer over the remaining portion of the first dielectric layer; and

forming a second contact feature having a second width in the second dielectric layer, the second width being substantially the same as the first width, wherein the second contact feature is coupled to the first contact feature.

2. The method of claim 1 wherein the removing the portion of the first dielectric layer includes performing a chemical mechanical polishing on the first dielectric layer.

3. The method of claim 1 wherein the forming the second contact feature includes forming a contact plug having a metal barrier layer on sidewalls and a bottom of the contact plug, wherein the metal barrier layer effects coupling between the first contact feature and the second contact feature.

4. The method of claim 1 further including forming a metal interconnect layer over the second contact feature, wherein the metal interconnect layer is coupled to the second contact feature.

5. The method of claim 1 wherein the replacing the dummy gate of the gate structure with the metal gate includes:

performing an etch back process to remove the dummy gate from the gate structure, thereby forming a trench; and

forming a work function metal layer and a filler metal layer in the trench, thereby forming the metal gate.

6. The method of claim 1 further including forming a first dummy contact feature in the first dielectric layer when forming the first contact feature, wherein the first dummy contact feature is coupled to the semiconductor substrate.

7. The method of claim 6 further including forming a second dummy contact feature in the second dielectric layer when forming the second contact feature, wherein the second dummy contact feature is coupled to the first dummy contact feature.

8. The method of claim 7 wherein the first dummy contact feature and the second dummy contact feature have a substantially same width.

9. The method of claim 7 wherein a pattern density of a region of the semiconductor substrate where the first contact feature and the second contact feature is formed is substantially less than a pattern density of another region of the semiconductor substrate where the first dummy contact feature and the second dummy contact feature is formed.