Multichip package structure using a constant voltage power supply

• US 8,405,118 B2
• Filed: 12/27/2010
• Issued: 03/26/2013
• Est. Priority Date: 10/22/2010
• Status: Active Grant

• Current Assignee: Paragon Semiconductor Lighting Technology Co., Ltd.
• Original Assignee: Paragon Semiconductor Lighting Technology Co., Ltd.
• Inventors: Chung, Chia-Tin, Dai, Shih-Neng
• Primary Examiner(s): Mandala, Victor A
• Application Number:
  US12/979,201
• Publication Number:
  US 20120097997A1
• Time in Patent Office: 820 Days
• Field of Search: 257/99, 257/100, 257/E33.056, 257/E33.058, 257/E33.059
• US Class Current: 257/99
• CPC Class Codes: F21K 9/00 Light sources using semiconductor devices as light-generating elements, e.g. using light-emitting diodes [LED] or lasers
• CPC Class Codes: F21V 23/005 the substrate is supporting also the light source
• CPC Class Codes: F21V 29/15 Thermal insulation
• CPC Class Codes: F21Y 2105/10 comprising a two-dimensional array of point-like light-generating elements
• CPC Class Codes: F21Y 2113/13 comprising an assembly of point-like light sources
• CPC Class Codes: F21Y 2115/10 Light-emitting diodes [LED]
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H01L 33/48 characterised by the semiconductor body packages
• CPC Class Codes: H01L 33/52 Encapsulations
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: H05K 1/0201 Thermal arrangements, e.g. for cooling, heating or preventing overheating
• CPC Class Codes: H05K 1/0209 External configuration of printed circuit board adapted for heat dissipation, e.g. lay-out of conductors, coatings
• CPC Class Codes: H05K 2201/09063 Holes or slots in insulating substrate not used for electrical connections
• CPC Class Codes: H05K 2201/09972 : Partitioned, e.g. portions of a PCB dedicated to different functions; Boundary lines therefore; Portions of a PCB being processed separately or differently
• CPC Class Codes: H05K 2201/10106 : Light emitting diode [LED]

Abstract

A multichip package structure includes a substrate unit, a light-emitting unit, a current-limiting unit, a frame unit and a package unit. The substrate unit includes a first chip-placing region and a second chip-placing region. The light-emitting unit includes a plurality of light-emitting chips electrically connected to the first chip-placing region. The current-limiting unit includes at least one current-limiting chip electrically connected to the second chip-placing region and the light-emitting unit. The frame unit includes a first annular colloid frame surrounding the light-emitting chips and a second annular colloid frame surrounding the current-limiting chip. The package unit includes a first package colloid body surrounded by the first annular colloid frame to cover the light-emitting chips and a second package colloid body surrounded by the second annular colloid frame to cover the current-limiting chip.

Claims

1. A multichip package structure, comprising:

a substrate unit including a substrate body having a first chip-placing region and a second chip-placing region formed on the top surface of the substrate body;

a light-emitting unit including a plurality of light-emitting chips electrically connected to and disposed on the first chip-placing region;

a current-limiting unit including at least one current-limiting chip electrically connected to and disposed on the second chip-placing region, wherein the current-limiting chip is electrically connected between the light-emitting unit and a constant voltage power supply, and a constant voltage generated by the constant voltage power supply is transmitted to the light-emitting unit through the current-limiting chip;

a frame unit including a first annular colloid frame and a second annular colloid frame surroundingly formed on the top surface of the substrate body, wherein the first annular colloid frame surrounds the light-emitting chips to form a first colloid position limiting space corresponding to the first chip-placing region, and the second annular colloid frame surrounds the current-limiting chip to form a second colloid position limiting space corresponding to the second chip-placing region; and

a package unit including a first package colloid body filled into the first colloid position limiting space to cover the light-emitting chips and a second package colloid body filled into the second colloid position limiting space to cover the current-limiting chip.

2. The multichip package structure of claim 1, wherein the substrate body includes a circuit substrate, a heat-dissipating layer disposed on the bottom surface of the circuit substrate, a plurality conductive pads disposed on the top surface of the circuit substrate, and an insulative layer disposed on the top surface of the circuit substrate to expose the conductive pads, wherein each light-emitting chip is a blue LED, the first package colloid body is a cured phosphor colloid or a cured transparent colloid, and the second package colloid body is a cured opaque colloid.

3. The multichip package structure of claim 1, wherein the first annular colloid frame has an arc shape formed on the top surface thereof, the first annular colloid frame has a radius tangent and the angle of the radius tangent relative to the top surface of the substrate body is between 40°

and 50°

, the maximum height of the first annular colloid frame relative to the top surface of the substrate body is between 0.3 mm and 0.7 mm, the width of the bottom side of the first annular colloid frame is between 1.5 mm and 3 mm, the thixotropic index of the first annular colloid frame is between 4 and 6, and the first annular colloid frame is formed by mixing inorganic additive with white thermohardening colloid.

4. The multichip package structure of claim 1, wherein the substrate unit includes a plurality of positive pads and negative pads disposed on the top surface of the substrate body, each light-emitting chip has a positive electrode and a negative electrode, the positive electrode of each light-emitting chip corresponds to at least two of the positive pads, and the negative electrode of each light-emitting chip corresponds to at least two of the negative pads.

5. The multichip package structure of claim 4, further comprising:

a conductive wire unit including a plurality of conductive wires, wherein every two conductive wires are respectively electrically connected between the positive electrode of each light-emitting chip and one of the at least two positive pads and between the negative electrode of each light-emitting chip and one of the at least two negative pads.

6. The multichip package structure of claim 1, wherein the first annular colloid frame and the second annular colloid frame are separated from each other by a predetermined distance, the first package colloid body and the second package colloid body are separated from each other by a predetermined distance, and the first annular colloid frame and the second package colloid body are separated from each other by a predetermined distance.

7. The multichip package structure of claim 1, wherein the second annular colloid frame surrounds the first annular colloid frame, the second package colloid body surrounds the first package colloid body, and the first annular colloid frame is connected with the second package colloid body.

8. The multichip package structure of claim 1, wherein the substrate unit includes at least one heat-insulating slot passing through the substrate body, and the heat-insulating slot is formed between the light-emitting unit and the current-limiting unit or between the first annular colloid frame and the second annular colloid frame.

9. A multichip package structure, comprising:

a substrate unit including a substrate body having two first chip-placing regions and a second chip-placing region formed on the top surface of the substrate body;

a light-emitting unit including at least one first light-emitting module for generating first color temperature and at least one second light-emitting module for generating second color temperature, wherein the first light-emitting module includes a plurality of first light-emitting chips electrically connected to and disposed on one of the first chip-placing regions, and the second light-emitting module includes a plurality of second light-emitting chips electrically connected to and disposed on the other first chip-placing region;

a current-limiting unit including at least one current-limiting chip electrically connected to and disposed on the second chip-placing region, wherein the current-limiting chip is electrically connected between the light-emitting unit and a constant voltage power supply, and a constant voltage generated by the constant voltage power supply is transmitted to the light-emitting unit through the current-limiting chip;

a frame unit including two first annular colloid frames and a second annular colloid frame surroundingly formed on the top surface of the substrate body, wherein the two first annular colloid frames respectively surround the first light-emitting module and the second light-emitting module to respectively form two first colloid position limiting spaces corresponding to the two first chip-placing regions, and the second annular colloid frame surrounds the current-limiting chip to form a second colloid position limiting space corresponding to the second chip-placing region; and

a package unit including two first package colloid bodies and a second package colloid body, wherein the two first package colloid bodies are respectively filled into the two first colloid position limiting spaces to respectively cover the first light-emitting module and the second light-emitting module, and the second package colloid body is filled into the second colloid position limiting space to cover the current-limiting chip.

10. A multichip package structure, comprising:

a substrate unit including a substrate body having two first chip-placing regions and a second chip-placing region formed on the top surface of the substrate body;

a light-emitting unit including at least one first light-emitting module for generating first color temperature and at least one second light-emitting module for generating second color temperature, wherein the first light-emitting module includes a plurality of first light-emitting chips electrically connected to and disposed on one of the first chip-placing regions, and the second light-emitting module includes a plurality of second light-emitting chips electrically connected to and disposed on the other first chip-placing region;

a current-limiting unit including at least one current-limiting chip electrically connected to and disposed on the second chip-placing region, wherein the current-limiting chip is electrically connected between the light-emitting unit and a constant voltage power supply, and a constant voltage generated by the constant voltage power supply is transmitted to the light-emitting unit through the current-limiting chip;

a frame unit including two first annular colloid frames and a second annular colloid frame surroundingly formed on the top surface of the substrate body, wherein one of the first annular colloid frames surrounds the other first annular colloid frame, the two first annular colloid frames respectively surround the first light-emitting module and the second light-emitting module to respectively form two first colloid position limiting spaces corresponding to the two first chip-placing regions, the second light-emitting module is disposed between the two first annular colloid frames, and the second annular colloid frame surrounds the current-limiting chip to form a second colloid position limiting space corresponding to the second chip-placing region; and

a package unit including two first package colloid bodies and a second package colloid body, wherein the two first package colloid bodies are respectively filled into the two first colloid position limiting spaces to respectively cover the first light-emitting module and the second light-emitting module, and the second package colloid body is filled into the second colloid position limiting space to cover the current-limiting chip.