Semiconductor device and method of manufacturing the same

• US 8,405,145 B2
• Filed: 06/03/2011
• Issued: 03/26/2013
• Est. Priority Date: 08/09/2006
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Matsuura, Hitoshi, Nakazawa, Yoshito, Kachi, Tsuyoshi, Yatsuda, Yuji
• Primary Examiner(s): Mandala, Victor A
• Application Number:
  US13/153,348
• Publication Number:
  US 20110233665A1
• Time in Patent Office: 662 Days
• Field of Search: 257/330, 257/332, 257/E29.257, 257/E29.26, 257/E27.091
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.

Claims

1. A semiconductor device comprising:

(a) a semiconductor substrate of a first conductivity type having a main surface and a back surface,

the main surface including a chip outermost region, a gate wire extension region arranged in a side direction of the main surface from the chip outermost region, an inactive cell region arranged in a side direction of the main surface from the gate wire extension region and an active cell region arranged in a side direction of the main surface from the inactive cell region;

(b) a gate trench formed in the inactive cell region and in the active cell region;

(c) a gate insulating film formed over an inner wall and a bottom portion of the gate trench;

(d) a gate electrode formed so as to fill the gate trench and electrically connected to a gate wire formed over the gate wire extension region;

(e) a source region, of the first conductivity type, formed in the active cell region so as to be adjacent to the gate electrode;

(f) a body region, of a second conductivity type different from the first conductivity type, formed in the active cell region so as to be deeper than a depth of the source region;

(g) a drain region of the first conductivity type formed in the back surface; and

(h) a first well region, of the second conductivity type, formed in the inactive cell region so as to be deeper than a depth of the body region and than a depth of the gate electrode,

wherein, in the inactive cell region, the body region is formed in the first well region, and

wherein the gate wire is integrally formed with the gate electrode.

2. The semiconductor device according to claim 1,

wherein the source region is not formed in the inactive cell region.

3. A semiconductor device comprising:

(a) a semiconductor substrate of a first conductivity type having a main surface and a back surface,

the main surface including a chip outermost region, a gate wire extension region arranged in a side direction of the main surface from the chip outermost region, an inactive cell region arranged in a side direction of the main surface from the gate wire extension region and an active cell region arranged in a side direction of the main surface from the inactive cell region;

(b) a gate trench formed in the inactive cell region and in the active cell region;

(c) a gate insulating film formed over an inner wall and a bottom portion of the gate trench;

(d) a gate electrode formed so as to fill the gate trench and electrically connected to a gate wire formed over the gate wire extension region;

(e) a source region, of the first conductivity type, formed in the active cell region so as to be adjacent to the gate electrode such that the source region is not formed in the inactive cell region;

(f) a body region, of a second conductivity type different from the first conductivity type, formed in the active cell region so as to be deeper than a depth of the source region; and

(g) a drain region of the first conductivity type formed in the back surface,

wherein the gate wire is integrally formed with the gate electrode.