Semiconductor device comprising multilayer interconnect structure with overlapping vias

• US 8,405,224 B2
• Filed: 12/30/2010
• Issued: 03/26/2013
• Est. Priority Date: 05/19/2009
• Status: Active Grant

• Current Assignee: Panasonic Semiconductor Solutions Co., Ltd. (Winbond Electronics Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Itoh, Kazuo
• Primary Examiner(s): Rizkallah, Kimberly
• Assistant Examiner(s): FERNANDES, ERROL V
• Application Number:
  US12/982,064
• Publication Number:
  US 20110089574A1
• Time in Patent Office: 817 Days
• Field of Search: 257/758, 257/774, 257/775
• US Class Current: 257/775
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device having a multilayer interconnect structure allowing heat in an interconnect layer at an intermediate level to be effectively dissipated is provided. A lower-layer interconnect (13), an intermediate interconnect (23), an upper-layer interconnect (33), a first contact via (15) formed to electrically connect the lower-layer interconnect (13) to the intermediate interconnect (23), and a second contact via (25) formed to electrically connect the intermediate interconnect (23) to the upper-layer interconnect (33) are provided. When viewed from above, the first and second contact vias (15, 25) both have a rectangular shape with their long sides extending in the same direction, and overlap with each other.

Claims

1. A semiconductor device comprising a multilayer interconnect structure which is formed above a substrate and includes first to Nth interconnect layers, where N is an integer equal to or larger than 4, stacked from the substrate in this order, the semiconductor device comprising:

a lower-layer interconnect formed in the first interconnect layer;

an intermediate interconnect formed in the second interconnect layer;

an upper-layer interconnect formed in the (N−

1)th interconnect layer;

a first contact via formed to electrically connect the lower-layer interconnect to the intermediate interconnect; and

a second contact via formed to electrically connect the intermediate interconnect to the upper-layer interconnect,

wherein when viewed from above, the first contact via and the second contact via both have a rectangular shape with their long sides extending in a same first direction parallel to a longitudinal axis of the lower-layer interconnect, and overlap with each other, and

wherein a dimension of the intermediate interconnect extending in the first direction is equal to or greater than a length of the long sides of each of the first contact via and the second contact via.

2. The semiconductor device of claim 1, wherein the lower-layer interconnect and the upper-layer interconnect both extend in the first direction, and

wherein a dimension of the intermediate interconnect extending in a second direction orthogonal to the first direction is equal to or greater than a length of short sides of each of the first contact via and the second contact via.

3. The semiconductor device of claim 1, wherein the lower-layer interconnect and the upper-layer interconnect both extend in the first direction.

4. The semiconductor device of claim 1, wherein each of the first contact via and the second contact via has the long sides whose length is 1.5 or more times that of short sides.

5. The semiconductor device of claim 1, wherein each of the first contact via and the second contact via has the long sides whose length is 5 or less times that of short sides.

6. The semiconductor device of claim 1, wherein the first contact via and the second contact via are identical in length of the long sides and short sides.

7. The semiconductor device of claim 1, wherein the first contact via and the second contact via are different from each other in length of at least one of the long sides and short sides.

8. The semiconductor device of claim 1, wherein when viewed from above, an area where the second contact via overlaps with the first contact via is 50% or more of an area of the first contact via.