System and method for calibrating output frequency in phase locked loop
First Claim
1. A Digital Calibration System (DCS) for a Phase Locked Loop (PLL), wherein the PLL comprises a PLL controller for outputting a tuning voltage in response to a reference signal and a feedback signal, and a voltage controlled oscillator (VCO) outputting the feedback signal as an output signal in response to the tuning voltage, the tuning voltage is used to determine whether the frequency of the output signal needs to be increased or decreased,the DCS comprising:
- a Tuning Voltage Controller (TVC) configured to set the tuning voltage to a value;
a Phase Difference Quantizer (PDQ) configured to output a phase difference after comparing a phase of the reference signal with a phase of the feedback signal; and
a Digital Controller (DC) configured to receive the phase difference of the PDQ and output a coarse tuning signal to adjust the feedback signal such that an average phase difference of the PDQ is 0.
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Accused Products
Abstract
A Digital Calibration System for a Phase Locked Loop includes a Tuning Voltage Controller configured to set the tuning voltage to a value; a Phase Difference Quantizer configured to output a phase difference after comparing a phase of the reference signal with a phase of the feedback signal; a Digital Controller configured to receive the phase difference of the PDQ and control a coarse tuning signal such that an average phase difference of the PDQ is 0; and a Frequency Calibration Logic configured to calibrate the feedback signal in response to the output of the DC.
19 Citations
12 Claims
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1. A Digital Calibration System (DCS) for a Phase Locked Loop (PLL), wherein the PLL comprises a PLL controller for outputting a tuning voltage in response to a reference signal and a feedback signal, and a voltage controlled oscillator (VCO) outputting the feedback signal as an output signal in response to the tuning voltage, the tuning voltage is used to determine whether the frequency of the output signal needs to be increased or decreased,
the DCS comprising: -
a Tuning Voltage Controller (TVC) configured to set the tuning voltage to a value; a Phase Difference Quantizer (PDQ) configured to output a phase difference after comparing a phase of the reference signal with a phase of the feedback signal; and a Digital Controller (DC) configured to receive the phase difference of the PDQ and output a coarse tuning signal to adjust the feedback signal such that an average phase difference of the PDQ is 0. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for calibrating the output frequency in a PLL, wherein the PLL comprises a PLL controller for outputting a tuning voltage in response to a reference signal and a feedback signal, a voltage controlled oscillator (VCO) for outputting the feedback signal as an output signal in response to the tuning voltage, the tuning voltage is used to determine if frequency of the output signal needs to be increased or decreased, comprising:
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setting the VCO tuning voltage to a value; quantizing the phase difference between a reference signal and a feedback signal; setting a coarse tuning to adjust the feedback signal in response to the phase difference such that an average of the phase difference is 0. - View Dependent Claims (11, 12)
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Specification