Methods of forming tunable capacitors

• US 8,424,176 B2
• Filed: 11/25/2009
• Issued: 04/23/2013
• Est. Priority Date: 11/25/2008
• Status: Active Grant

• Current Assignee: Ensurge Micropower ASA
• Original Assignee: Kovio Incorporated (Ensurge Micropower ASA)
• Inventors: Smith, Patrick, Wang, Zhigang
• Primary Examiner(s): TRINH, MINH N
• Application Number:
  US12/626,562
• Publication Number:
  US 20100296225A1
• Time in Patent Office: 1,245 Days
• Field of Search: 29 2541- 2542, 296/00, 295921-5924, 343/700.MS, 3435721-5725, 361/303, 361/306.3, 361/312
• US Class Current: 29/25.42
• CPC Class Codes: G08B 13/2437 Tag layered structure, processes for making layered tags
• CPC Class Codes: H01L 27/016 Thin-film circuits
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0808 Varactor diodes
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 28/88 made by patterning layers, e.g. by etching conductive layers
• CPC Class Codes: Y10T 29/43 Electric condenser making
• CPC Class Codes: Y10T 29/435 Solid dielectric type
• CPC Class Codes: Y10T 29/49002 Electrical device making
• CPC Class Codes: Y10T 29/49016 Antenna or wave energy "plumbing" making

Abstract

The present invention relates to methods of making and using tunable capacitors and devices. Using the methods described, one or more secondary tunable capacitors can be connected to a primary capacitor by printing a connector conducting layer or feature to obtain a desired net capacitance. Digitally printing the connector conducting layer allows the number of secondary capacitors connected into the circuit to be determined during the integrated circuit fabrication process, without the need for individual masks connecting the appropriate number of secondary capacitors. This provides an in-process or post-process trimming method to obtain the desired precision and accuracy for capacitors. Various sizes and combinations of secondary capacitors can be connected to obtain high precision capacitors and/or improved matching of capacitance values.

Claims

1. A method of forming a capacitor, comprising:

a) depositing a main capacitor dielectric layer on a conductive substrate;

b) forming a main upper electrode and a plurality of tuning electrodes on said main capacitor dielectric layer, wherein forming the main upper electrode and the tuning electrodes comprises printing a metal precursor ink on the main capacitor dielectric layer in a pattern corresponding to the main upper electrode; and

c) printing one or more conductive features electrically connecting said main upper electrode to at least one of said tuning electrodes.

2. The method of claim 1, wherein said conductive substrate comprises a main lower electrode.

3. The method of claim 1, wherein the conductive substrate comprises a metal sheet comprising aluminum, titanium, copper, silver, chromium, molybdenum, tungsten, nickel, gold, palladium, platinum, zinc, iron, or an alloy thereof.

4. The method of claim 1, wherein the conductive substrate comprises a metal foil comprising aluminum, copper, or stainless steel.

5. The method of claim 1, further comprising cleaning or smoothing the conductive substrate before depositing the main capacitor dielectric layer thereon.

6. The method of claim 1, wherein printing the one or more conductive features comprises printing a conductive seed layer and electroplating or electrolessly plating a bulk conductor on the conductive seed layer.

7. The method of claim 1, wherein printing the one or more conductive features comprises digitally printing a metal precursor material in a desired pattern.

8. The method of claim 1, wherein the one or more conductive features comprise a conductive metal, a nitride, or a metal alloy.

9. The method of claim 1, further comprising forming a passivation layer on the substrate by coating an upper surface of the substrate with one or more inorganic barrier layers and/or one or more organic barrier layers.

10. A method of making a device comprising:

a) forming a capacitator by (i) depositing a main capacitor dielectric layer on a conductive substrate, (ii) forming a main upper electrode and a plurality of tuning electrodes on said main capacitor dielectric layer, and (iii) printing one or more conductive features electrically connecting said main upper electrode to at least one of said tuning electrodes;

b) forming a second dielectric layer on at least part of the substrate; and

c) forming an antenna and/or inductor electrically connected to said conducting feature and said conductive substrate.

11. The method of claim 10, wherein forming said main upper electrode comprises selectively depositing a conducting layer on said main capacitor dielectric layer.

12. The method of claim 11, wherein depositing said conducting layer comprises printing a metal precursor ink in a pattern corresponding to said main upper electrode.

13. The method of claim 12, further comprising drying said metal precursor ink and annealing said dried precursor to form said conducting layer.

14. The method of claim 12, wherein printing the metal precursor ink comprises inkjet printing, gravure printing, screen printing, offset printing, flexography, laser writing, laser forward transfer, or local laser chemical vapor deposition.

15. The method of claim 12, wherein the metal precursor ink comprises nanoparticles, salts, clusters, complexes, compounds, nitrides, and/or silicides of an elemental metal or metal alloy.

16. The method of claim 12, further comprising etching the dielectric layer before printing the metal precursor ink.

17. The method of claim 10, wherein forming the main upper electrode and the plurality of tuning electrodes comprises printing a metal seed layer on the main capacitor dielectric layer and depositing a bulk metal on the seed layer by electroplating or electroless plating.

18. The method of claim 10, wherein forming the main upper electrode and the plurality of tuning electrodes comprises depositing one or more semiconductor compounds on the main capacitor dielectric layer and recrystallizing the semiconductor material.

19. The method of claim 18, wherein the semiconductor material is lightly or heavily doped.

20. The method of claim 10, wherein depositing the main capacitor dielectric layer comprises selectively printing a liquid-phase dielectric precursor material on the conductive substrate to form a pattern, and the method further comprises drying and/or curing the dielectric precursor.

21. The method of claim 10, wherein depositing the main capacitor dielectric layer comprises covering the entire conductive substrate with a dielectric precursor ink and curing to form the dielectric layer, and the method further comprises etching the dielectric layer to form a pattern using subsequently formed structures as a mask.

22. The method of claim 10, wherein forming the second dielectric layer comprises selectively printing a dielectric material in a pattern including contact holes therein, the contact holes exposing at least a portion of the one or more conductive features and/or the conductive substrate.

23. The method of claim 10, wherein forming the antenna and/or inductor comprises selectively printing a metal precursor ink on the second dielectric layer in a pattern corresponding to the antenna and/or inductor.

24. A method of forming a capacitor, comprising:

a) depositing a main capacitor dielectric layer on a conductive substrate;

b) forming a main upper electrode and a plurality of tuning electrodes on said main capacitor dielectric layer, wherein forming the main upper electrode and the plurality of tuning electrodes comprises printing a metal seed layer on the main capacitor dielectric layer and depositing a bulk metal on the seed layer by electroplating or electroless plating; and

c) printing one or more conductive features electrically connecting said main upper electrode to at least one of said tuning electrodes.

25. A method of forming a capacitor, comprising:

a) depositing a main capacitor dielectric layer on a conductive substrate;

b) forming a main upper electrode and a plurality of tuning electrodes on said main capacitor dielectric layer, wherein forming the main upper electrode and the plurality of tuning electrodes comprises depositing one or more semiconductor compounds on the main capacitor dielectric layer and recrystallizing the semiconductor material; and

c) printing one or more conductive features electrically connecting said main upper electrode to at least one of said tuning electrodes.

26. A method of forming a capacitor, comprising:

a) depositing a main capacitor dielectric layer on a conductive substrate, wherein depositing the main capacitor dielectric layer comprises selectively printing a liquid-phase dielectric precursor material on the conductive substrate to form a pattern, and the method further comprises drying and/or curing the dielectric precursor;

b) forming a main upper electrode and a plurality of tuning electrodes on said main capacitor dielectric layer; and

c) printing one or more conductive features electrically connecting said main upper electrode to at least one of said tuning electrodes.

27. A method of forming a capacitor, comprising:

a) depositing a main capacitor dielectric layer on a conductive substrate, wherein depositing the main capacitor dielectric layer comprises covering the entire conductive substrate with a dielectric precursor ink and curing to form the dielectric layer, and the method further comprises etching the dielectric layer to form a pattern using subsequently formed structures as a mask;

b) forming a main upper electrode and a plurality of tuning electrodes on said main capacitor dielectric layer; and

c) printing one or more conductive features electrically connecting said main upper electrode to at least one of said tuning electrodes.

28. A method of forming a capacitor, comprising:

a) depositing a main capacitor dielectric layer on a conductive substrate;

b) forming a main upper electrode and a plurality of tuning electrodes on said main capacitor dielectric layer; and

c) printing one or more conductive features electrically connecting said main upper electrode to at least one of said tuning electrodes, wherein printing the one or more conductive features comprises printing a conductive seed layer and electroplating or electrolessly plating a bulk conductor on the conductive seed layer.