Storage system comprising flash memory modules subject to plural types of wear-leveling processes
First Claim
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1. A storage system comprising:
- a plurality of flash memory modules, each of the plurality of flash memory modules comprising at least one flash memory chip and a memory controller, the memory controller managing a plurality of blocks provided with the at least one flash memory chip and controlling a first wear-leveling process of the plurality of blocks so that erase counts between the plurality of blocks may be leveled; and
a storage controller coupled to the plurality of flash memory modules, and managing a logical volume and controlling read/write requests from a host computer to the logical volume,the storage controller controlling a second wear-leveling process exchanging data between at least one block of a first flash memory module of the plurality of flash memory modules and at least one block of a second flash memory module of the plurality of flash memory modules so that erase counts between the plurality of flash memory modules may be leveled.
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Abstract
A storage system uses a plurality of flash memory modules and a storage controller. Each of the plurality of flash memory modules comprises a memory controller and at least one flash memory chip. The memory controller manages a plurality of blocks provided with the at least one flash memory chip and controls a first wear-leveling process for leveling erase counts between the plurality of blocks. The storage controller, coupled to the plurality of flash memory modules, controls data sent from a host computer to be sent to a flash memory module of the plurality of flash memory modules. The storage controller controls a second wear-leveling process exchanging data between at least one block of a first flash memory module of the plurality of flash memory modules and at least one block of a second flash memory module of the plurality of flash memory modules.
20 Citations
23 Claims
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1. A storage system comprising:
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a plurality of flash memory modules, each of the plurality of flash memory modules comprising at least one flash memory chip and a memory controller, the memory controller managing a plurality of blocks provided with the at least one flash memory chip and controlling a first wear-leveling process of the plurality of blocks so that erase counts between the plurality of blocks may be leveled; and a storage controller coupled to the plurality of flash memory modules, and managing a logical volume and controlling read/write requests from a host computer to the logical volume, the storage controller controlling a second wear-leveling process exchanging data between at least one block of a first flash memory module of the plurality of flash memory modules and at least one block of a second flash memory module of the plurality of flash memory modules so that erase counts between the plurality of flash memory modules may be leveled. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A storage system comprising:
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a plurality of flash memory modules, each of the plurality of flash memory modules comprising a memory controller and at least one flash memory chip, the memory controller managing a plurality of blocks provided with the at least one flash memory chip and controlling a first wear-leveling process for leveling erase counts between the plurality of blocks; and a storage controller coupled to the plurality of flash memory modules, and controlling data sent from a host computer to be sent to a flash memory module of the plurality of flash memory modules, the storage controller controlling a second wear-leveling process exchanging data between at least one block of a first flash memory module of the plurality of flash memory modules and at least one block of a second flash memory module of the plurality of flash memory modules. - View Dependent Claims (13, 14, 15, 16, 17)
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18. A storage system comprising:
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a plurality of flash memory modules, each of the plurality of flash memory modules comprising a memory controller and at least one flash memory chip, the memory controller managing a plurality of blocks provided with the at least one flash memory chip and controlling a first wear-leveling process exchanging data between at least two of the plurality of blocks; and a storage controller coupled to the plurality of flash memory modules, and having a cache memory and controlling data sent from a host computer to be transferred to a flash memory module of the plurality of flash memory modules via the cache memory, the storage controller controlling a second wear-leveling process exchanging data between at least one block of a first flash memory module of the plurality of flash memory modules and at least one block of a second flash memory module of the plurality of flash memory modules. - View Dependent Claims (19, 20, 21, 22, 23)
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Specification
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Current AssigneeHitachi, Ltd.
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Original AssigneeHitachi, Ltd.
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InventorsTanaka, Katsuya, Shimada, Kentaro
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Primary Examiner(s)Verbrugge, Kevin
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Application NumberUS13/151,015Publication NumberTime in Patent Office692 DaysField of SearchNoneUS Class Current711/103CPC Class CodesG06F 12/0246 in block erasable memory, e...G06F 2212/1036 Life time enhancementG06F 2212/7208 Multiple device management,...G06F 2212/7211 Wear levelingG06F 3/0601 Interfaces specially adapte...G06F 3/0664 at device level, e.g. emula...
