Method and apparatus for storing data in a NAND flash memory

• US 8,437,189 B1
• Filed: 02/15/2012
• Issued: 05/07/2013
• Est. Priority Date: 12/20/2006
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Montierth, Mark D., Briggs, Randall D., Keithley, Douglas G.
• Primary Examiner(s): Mai, Son
• Application Number:
  US13/397,504
• Time in Patent Office: 447 Days
• Field of Search: 365/185.09
• US Class Current: 365/185.09
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

Semi-volatile NAND flash memory systems, apparatuses, and methods for use are described herein. According to various embodiments, a semi-volatile NAND flash memory may be partitioned into various retention regions. Other embodiments may be described and claimed.

Claims

1. A method comprising:

partitioning a NAND flash memory into a plurality of retention regions including a first retention region and a second retention region, wherein the second retention region has a longer data retention requirement than the first retention region;

storing data in a memory block of the first retention region;

determining whether the data stored in the memory block of the first retention region needs to be refreshed; and

in response to determining that the data stored in the memory block of the first retention region needs to be refreshed, performing a refresh operation on the data stored in the memory block of the first retention region, wherein performing the refresh operation on the data stored in the memory block of the first retention region comprises

(i) if the memory block of the first retention region has endured a predetermined number of erase/write cycles, relocating the data from the memory block of the first retention region to a memory block of the second retention region so that the data relocated to the memory block of the second retention region can be stored in accordance with the longer data retention requirement associated with the second retention region, and

(ii) if the first memory block has endured less than the predetermined number of erase/write cycles, refreshing the data in the memory block of the first retention region.

2. The method of claim 1, wherein determining that the data written in the memory block of the first retention region needs to be refreshed comprises:

determining that the data written in the memory block of the first retention region has not been refreshed for a predetermined period of time.

3. The method of claim 2, wherein the predetermined period of time is based on a number of erase/write cycles endured by the memory block of the first retention region.

4. The method of claim 1, wherein refreshing the data in the memory block of the first retention region comprises:

reading the data from the memory block of the first retention region; and

rewriting the data to the memory block of the first retention region.

5. The method of claim 1, wherein the data is transient data.

6. The method of claim 1, wherein the NAND flash memory comprises a semi-volatile NAND flash memory.

7. A device comprising:

a NAND flash memory partitioned into a plurality of retention regions including a first retention region and a second retention region, wherein the second retention region has a longer data retention requirement than the first retention region; and

a memory controller configured to

store data in a memory block of a first retention region,

determine whether the data written in the memory block of the first retention region needs to be refreshed, and

in response to determining that the data written in the memory block of the first retention region needs to be refreshed, perform a refresh operation on the data stored in the memory block of the first retention region, wherein performing the refresh operation on the data stored in the memory block of the first retention region comprises

(i) if the memory block of the first retention region has endured a predetermined number of erase/write cycles, relocate the data from the memory block of the first retention region to a memory block of the second retention region so that the data relocated to the memory block of the second retention region can be stored in accordance with the longer data retention requirement associated with the second retention region, and

(ii) if the memory block of the first retention region has endured less than the predetermined number of erase/write cycles, refresh the data in the memory block.

8. The device of claim 7, wherein the memory controller is configured to determine that the data written in the memory block of the first retention region needs to be refreshed by:

determining that the data written in the first memory block has not been refreshed for a predetermined period of time.

9. The device of claim 8, wherein the predetermined period of time is based on a number of write/erase cycles endured by the memory block of the first retention region.

10. The device of claim 7, wherein the memory controller is configured to refresh the data in the memory block of the first retention region by:

reading the data from the memory block of the first retention region; and

rewriting the data to the memory block of the first retention region.

11. The device of claim 7, wherein the data is transient data.

12. The device of claim 7, wherein the NAND flash memory is a semi-volatile NAND flash memory.

13. The device of claim 7, wherein the NAND flash memory is implemented on a single chip.

14. The device of claim 7, wherein the device comprises a printer.

15. The device of claim 7, wherein the device comprises a compact disc (CD) player.