Flexible bus architecture for monitoring and control of battery pack

• US 8,438,426 B2
• Filed: 08/10/2012
• Issued: 05/07/2013
• Est. Priority Date: 08/31/2010
• Status: Active Grant

• Current Assignee: O2 Micro International Limited (O2 Micro Incorporated)
• Original Assignee: O2 Micro International Limited (O2 Micro Incorporated)
• Inventors: Li, Guoxing, Zeng, Xiaojun, Xiao, Anquan, Hou, Xiaohua
• Primary Examiner(s): GUYTON, PHILIP A
• Application Number:
  US13/572,193
• Publication Number:
  US 20120303997A1
• Time in Patent Office: 270 Days
• Field of Search: 714/4.5, 714/43, 320/122, 320/126
• US Class Current: 714/43
• CPC Class Codes: G06F 11/221 to test buses, lines or interfaces, e.g. stuck-at or open line faults
• CPC Class Codes: H02J 7/0014 Circuits for equalisation of charge between batteries
• CPC Class Codes: H02J 7/0048 Detection of remaining charge capacity or state of charge [SOC]
• CPC Class Codes: Y02T 10/70 Energy storage systems for electromobility, e.g. batteries

Abstract

A method for diagnosing a control system for a stacked battery. The control system comprises a plurality of processors, a plurality of controllers, and a monitoring unit (control unit). The method comprises sending a diagnostic information from the central unit to a top processor of the plurality of processors, transmitting a return information from the top processor of the plurality of processors to the central unit, comparing the diagnostic information sent from the central unit with the return information received by the central unit, and indicating a communication problem if the diagnostic information sent from the central unit is different from the return information received by the central unit. The steps are repeated by eliminating the top processor from a previous cycle and assigning a new top processor if there is no problem with the reconfigurable communication system.

Claims

1. A method for diagnosing a control system for a stacked battery, the control system having a central unit in communication with a plurality of processors and a plurality of controllers, the plurality of processors being coupled in sequence and being in communication with the plurality of controllers through a plurality of lateral buses, the method comprising:

a) sending diagnostic information from the central unit to a top processor of the plurality of processors;

b) transmitting return information from the top processor of the plurality of processors to the central unit;

c) comparing the diagnostic information sent from the central unit with the return information received by the central unit;

d) indicating a communication problem if the diagnostic information sent from the central unit is different from the return information received by the central unit;

m) identifying, by performing steps a) to d), a problematic bus where the communication problem occurs; and

n) activating at least one bus of the plurality of lateral buses according to the identified problematic bus.

2. The method of claim 1, further comprising the steps of:

f) sending the diagnostic information from the top processor of the plurality of processors to the controller with which it is in communication; and

g) receiving the return information at the top processor of the plurality of processors from the controller with which it is in communication.

3. The method of claim 1, wherein the step a) further comprises:

h) sending the diagnostic information from the central unit to a top controller of the plurality of controllers.

4. The method of claim 3, wherein the diagnostic information being sent from the central unit to the top controller of the plurality of controllers without passing through the plurality of processors.

5. The method of claim 3, further comprising the step of reconfiguring the control system for the diagnostic information to by-pass the plurality of processors.

6. The method of claim 1, wherein the step m) further comprises:

i) sending diagnostic information from the central unit to a diagnostic processor of the plurality of processors;

j) transmitting the diagnostic information from the diagnostic processor of the plurality of processors to the central unit that are below the diagnostic processor;

k) comparing the diagnostic information sent from the central unit to the diagnostic processor with the diagnostic information received by the central unit from the diagnostic processor; and

l) determining that the communication system below the diagnostic processor is in working condition when the diagnostic information sent from the central unit to the diagnostic processor is not different from the diagnostic information received by the central unit from the diagnostic processor.

7. The method of claim 6, wherein the top processor is one level higher than the diagnostic processor, and wherein the step m) further comprises:

o) determining that communication between the diagnostic processor and the top processor is not in working condition if the following conditions occur;

the diagnostic information sent from the central unit to the top processor is different from the return information received by the central unit from the top processor; and

the diagnostic information sent from the central unit to the diagnostic processor is not different from the diagnostic information received by the central unit from the diagnostic processor.

8. A system for controlling a plurality of battery packs, each battery pack having a plurality of battery cells coupled in series, the system comprising:

a plurality of processors connected in sequence, each processor being in communication with an adjacent processor through a first bus;

a plurality of controllers, connected in sequence, for balancing loads of the plurality of battery cells, each controller being in communication with an adjacent controller through a second bus, and the plurality of controllers being in communication with the plurality of processors through a plurality of lateral buses; and

a control unit for identifying a problematic bus having a communication problem, and reconfiguring communication path among the pluralities of processors and controllers by activating at least one bus of the plurality of lateral buses according to the identified problematic bus.

9. The system of claim 8, further comprising a plurality of isolators in communication with the plurality of processors and the control unit.

10. The system of claim 9, wherein the plurality of isolators being in communication with the plurality of processors are connected in a cascade fashion.

11. A system, for configuring communication path in a stacked battery, comprising:

a plurality of processors connected in sequence, each processor being in communication with an adjacent processor through a first bus;

a plurality of controllers connected in sequence, each controller being in communication with an adjacent controller through a second bus;

a plurality of lateral buses coupled between the plurality of processors and the plurality of controllers; and

a control unit for sending diagnostic information through the plurality of processors and the plurality of controllers to identify a problematic bus having a communication problem, and for activating at least one bus of the plurality of lateral buses to by-pass the identified problematic bus.

12. The system of claim 11, wherein the each processor includes an analog digital converter for monitoring a condition of a plurality of battery cells in the stacked battery.

13. The system of claim 12, wherein a controller of the plurality of controllers balances loads of the plurality of battery cells in the stacked battery.

14. The system of claim 11, wherein the each controller comprises a top bus interface and a bottom bus interface, and wherein

a first controller communicates with a second controller below the first controller through the bottom bus interface of the first controller, the second bus, and the top bus interface of the second controller.

15. The system of claim 11, further comprising:

a plurality of isolators coupled to the plurality of controllers, wherein two adjacent controllers of the plurality of controllers communicate with each other through one of the plurality of isolators.

16. The system of claim 15, wherein the each controller is coupled to an isolator of the plurality of isolators via the second bus.

17. The system of claim 15, wherein the isolators are coupled in a fashion that is selected from the group consisting of a star fashion and a cascade fashion.

18. The system of claim 11, wherein the each processor communicates with a controller of the plurality of controllers via a corresponding lateral bus of the plurality of lateral buses when the corresponding lateral bus is activated.

19. The system of claim 11, wherein if the communication problem occurs in the first bus between a first processor and a second processor that is one level lower than the first processor, the control unit communicates with the first processor through at least one controller of the plurality of controllers and through the activated at least one lateral bus.

20. The system of claim 11, wherein if the communication problem occurs in the second bus between a first controller and a second controller that is one level lower than the first controller, the control unit communicates with the first controller through at least one processor of the plurality of processors and through the activated at least one lateral bus.