Integrated circuit having a scan chain and testing method for a chip

• US 8,438,439 B2
• Filed: 01/26/2012
• Issued: 05/07/2013
• Est. Priority Date: 10/12/2009
• Status: Active Grant

• Current Assignee: Actions (Zhuhai) Technology Co., Limited
• Original Assignee: Actions Semiconductor Company Limited
• Inventors: Xie, Wuhong
• Primary Examiner(s): TRIMMINGS, JOHN P
• Application Number:
  US13/359,015
• Publication Number:
  US 20120124437A1
• Time in Patent Office: 467 Days
• Field of Search: None
• US Class Current: 714/726
• CPC Class Codes: G01R 31/3172 Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing
• CPC Class Codes: G01R 31/318533 using scanning techniques, e.g. LSSD, Boundary Scan, JTAG

Abstract

An IC having a scan chain and a testing method for a chip, comprising a first interface group, a second interface group and a scan data selector. The first interface group and the second interface group each comprise at least two input/output (I/O) interfaces which can be packaged as external pins of the IC. The I/O interfaces of the first interface group are connected to input terminals of the scan data selector in one-to-one correspondence, and an output terminal of the scan data selector is connected to a scan data input terminal of the scan chain. A scan data output terminal of the scan chain is connected to the I/O interfaces of the second interface group.

Claims

1. An integrated circuit (IC) having a scan chain, further comprising a first interface group, a second interface group and a scan data selector;

the first interface group and the second interface group each comprise at least two input/output (I/O) interfaces which can be packaged as external pins of the IC;

the I/O interfaces of the first interface group are connected to input terminals of the scan data selector in one-to-one correspondence, and an output terminal of the scan data selector is connected to a scan data input terminal of the scan chair;

a scan data output terminal of the scan chain is directly connected to the I/O interfaces of the second interface group; and

the scan data selector is configured to, according to a package type indicating signal inputted to a control terminal thereof, select data in one of the I/O interfaces of the first interface group that corresponds to the package type indicating signal for output to the scan data input terminal,

wherein in each package type of the IC, at least one of the I/O interfaces of the first interface group is packaged as an external pin, and at least one of the I/O interfaces of the second interface group is packaged as an external pin.

2. The IC of claim 1, further comprising a clock interface group and as clock signal selector;

the clock interface group comprises at least two I/O interfaces that can be packaged as external pins of the IC;

the I/O interfaces of the dock interface group are connected to input terminals of the clock signal selector in one-to-one correspondence, and an output terminal of the clock signal selector is connected to a scan clock input terminal of the scan chain; and

the clock signal selector is configured to, according to a package type indicating signal inputted to a control terminal thereof, select a clock signal in one of the I/O interfaces of the clock interface group that corresponds to the package type indicating signal for output to the scan clock input terminal of the scan chain.

3. The IC of claim 1, further comprising an enable interface group and an enable signal selector;

the enable interface group comprises at least two I/O interfaces that can be packaged as external pins of the IC;

the I/O interfaces of the enable interface group are connected to input terminals of the enable signal selector in one-to-one correspondence, and an output terminal of the enable signal selector is connected to a scan enable input terminal of the scan chain; and

the enable signal selector is configured to, according to a package type indicating signal inputted to a control terminal thereof, select an enable signal in one of the I/O interfaces of the enable interface group that corresponds to the package type indicating signal for output to the scan enable input terminal of the scan chain.

4. The IC of claim 2, further comprising an enable interface group and an enable signal selector;

the enable interface group comprises at least two I/O interfaces that can be packaged as external pins of the IC;

the I/O interfaces of the enable interface group are connected to input terminals of the enable signal selector in one-to-one correspondence, and an output terminal of the enable signal selector is connected to a scan enable input terminal of the scan chain; and

the enable signal selector is configured to, according to a package type indicating signal inputted to a control terminal thereof, select an enable signal in one of the I/O interfaces of the enable interface group that corresponds to the package type indicating signal for output to the scan enable input terminal of the scan chain.

5. An IC having a scan chain, comprising a plurality of scan chain units, each of which comprises a first interface group, a second interface group, a scan chain and a scan data selector;

the first interface group and the second interface group each comprise at least two I/O interfaces which can be packaged as external pins of the IC;

the I/O interfaces of the first interface group are connected to input terminals of the scan data selector in one-to-one correspondence, and an output terminal of the scan data selector is connected to a scan data input terminal of the scan chain;

a scan data output terminal of the scan chain is directly connected to the I/O interfaces of the second interface group; and

the scan data selector is configured to, according to a package type indicating signal inputted to a control terminal thereof, select data in one of the I/O interfaces of the first interface group that corresponds to the package type indicating signal for output,

wherein in each package type of the IC, at least one of the I/O interfaces of the first interface group is packaged as an external pin, and at least one of the I/O interfaces of the second interface group is packaged as an external pin.

6. The IC of claim 5, further comprising a clock control unit which comprises a clock interface group and a clock signal selector;

the clock interface group comprises at least two I/O interfaces that can be packaged as external pins of the IC;

the I/O interfaces of the clock interface group are connected to input terminals of the clock signal selector in one-to-one correspondence, and an output terminal of the clock signal selector is connected to a scan clock input terminal of the scan chain; and

the clock signal selector is configured to, according to a package type indicating signal inputted to a control terminal thereof, select a clock signal in one of the I/O interfaces of the dock interface group that corresponds to the package type indicating signal for output to the scan dock input terminal of the scan chain.

7. The IC of claim 5, further comprising an enable control unit which comprises an enable interface group and an enable signal selector;

the enable interface group comprises at least two I/O interfaces that can be packaged as external pins of the IC;

the I/O interfaces of the enable interface group are connected to input terminals of the enable signal selector in one-to-one correspondence, and an output terminal oldie enable signal selector is connected to a scan enable input terminal of the scan chain; and

the enable signal selector is configured to, according to a package type indicating signal inputted to a control terminal thereof, select an enable signal in one of the I/O interfaces of the enable interface group that corresponds to the package type indicating signal for output to the scan enable input terminal of the scan chain.

8. The IC of claim 6, further comprising an enable control unit which comprises an enable interface group and an enable signal selector;

the enable interface group comprises at least two I/O interfaces that can be packaged as external pins of the IC;

the I/O interfaces of the enable interface group are connected to input terminals of the enable signal selector in one-to-one correspondence, and an output terminal of the enable signal selector is connected to a scan enable input terminal of the scan chain; and

the enable signal selector is configured to according to a package type indicating signal inputted to a control terminal thereof, select an enable signal in one of the I/O interfaces of the enable interface group that corresponds to the package type indicating signal for output to the scan enable input terminal of the scan chain.

9. The IC of claim 5, wherein the number of the I/O interfaces in the first interface group is the same or different for each of the scan chain units, and the number of the I/O interlaces in the second interface group is the same or different for each of the scan chain units.

10. The IC of claim 6, wherein the number of the I/O interfaces in the first interface group is the same or different for each of the scan chain units, and the number of the interfaces in the second interface group is the same or different for each of the scan chain units.

11. A testing method for a chip, wherein the chip comprises a first pin, a second pin, a scan chain, a first interface group, a second interface group and a scan data selector, the first interface, group and the second interface group each comprise at least two I/O interfaces, one of the ISO interfaces of the first interface group is connected to the first pin, and one of the ISO interfaces of the second interface group is connected to the second pin;

the ISO interfaces of the first interface group are connected to input terminals of the scan data selector in one-to-one correspondence, an output terminal of the scan data selector is connected to a scan data input terminal of the scan chain, and a scan data output terminal of the scan chain is directly connected to the ISO interfaces of the second interface group,

wherein in each package type of the IC, at least one of the ISO interfaces of the first interface group is packaged as an external pin, and at least one of the I/O interfaces of the second interface group is packaged as an external pin;

the testing method comprises;

inputting test input data from the first pin;

selecting, by the scan data selector, the test input data for input into the scan data input terminal according to package type information of the chip;

outputting test output data from the scan data output terminal by the scan chain in response to the test input data; and

reading the test output data from the second pin.