Strings of memory cells having string select gates, memory devices incorporating such strings, and methods of accessing and forming the same

• US 8,441,855 B2
• Filed: 01/14/2011
• Issued: 05/14/2013
• Est. Priority Date: 01/14/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Liu, Zengtao
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US13/006,762
• Publication Number:
  US 20120182805A1
• Time in Patent Office: 851 Days
• Field of Search: 365/185.17, 365/185.01, 365/185.11, 365/185.14
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

Strings of memory cells having a string select gate configured to selectively couple ends of a string to a data line and a source line concurrently, memory devices incorporating such strings and methods for accessing and forming such strings are provided. For example, non-volatile memory devices are disclosed that utilize vertical structure NAND strings of serially-connected non-volatile memory cells. One such string including two or more serially-connected non-volatile memory cells where each end of the string shares a string select gate with the other end of the string is disclosed.

Claims

1. A string of memory cells, comprising:

one or more first memory cells;

one or more second memory cells; and

a string select gate having a first channel structure and a second channel structure;

wherein the one or more first memory cells and the one or more second memory cells are serially-connected to collectively define the string of memory cells; and

wherein the string select gate is configured to concurrently selectively couple a first end of the string of memory cells to a data line through the first channel structure and a second end of the string of memory cells to a source line through the second channel structure.

2. The memory device of claim 1, wherein the string of serially-connected memory cells comprises a NAND string of serially-connected memory cells.

3. The memory device of claim 1, wherein the string of serially-connected memory cells comprises a first stack of vertically formed memory cells and a second stack of vertically formed memory cells.

4. The memory device of claim 3, wherein the first stack and the second stack of memory cells each comprise an equal number of memory cells.

5. The memory device of claim 4, wherein the number of memory cells in the first stack and the second stack of memory cells is equal to 2^N, where N is an integer.

6. The memory device of claim 3, wherein the string select gate is formed between the first end and the second end of the string.

7. The memory device of claim 3, wherein the first stack and the second stack are formed on a semiconductor substrate and are further formed adjacent to each other.

8. The memory device of claim 3, further comprising a control gate formed at a bottom of the first stack and at a bottom of the second stack where the control gate is configured to selectively couple the bottom of each stack together.

9. The memory device of claim 3, wherein the first stack and the second stack of memory cells each comprise one or more non-active memory cells.

10. The memory device of claim 1, wherein the string select gate comprises a single gate comprising two channel regions.

11. The memory device of claim 1, wherein the string of serially-connected memory cells is configured in a U shaped arrangement.

12. The memory device of claim 1, further comprising:

a drain select gate formed at the first end of the string; and

a source select gate formed at the second end of the string;

wherein the string select gate is further configured to concurrently selectively couple both the drain select gate to the data line and the source select gate to the source line.

13. A memory device, comprising:

a data line;

a source line;

a first stack of series coupled memory cells;

a second stack of series coupled memory cells adjacent the first stack where a first end of the first stack is selectively coupled to a first end of the second stack; and

a string select gate formed between a second end of the first stack and a second end of the second stack and having a first channel structure and a second channel structure, wherein the string select gate is configured to concurrently selectively couple the second end of the first stack to the data line through the first channel structure and the second end of the second stack to the source line through the second channel structure.

14. The memory device of claim 13, wherein the first stack of series coupled memory cells comprises an equal number of memory cells as the second stack of series coupled memory cells.

15. The memory device of claim 13, wherein the first stack and the second stack each comprise vertically formed columns formed on a semiconductor substrate.

16. A memory device, comprising:

a data line;

a source line;

a first string of series coupled memory cells formed along a first side of a first column and along a side of a second column, where the side of the second column is adjacent to the first side of the first column;

a second string of series coupled memory cells formed along a second side of the first column and along a side of a third column, where the side of the third column is adjacent to the second side of the first column;

a first string select gate formed between a top end of the first column and a top end of the second column and having a first channel structure between the first string select gate and the first column and a second channel structure between the first string select gate and the second column; and

a second string select gate formed between a top end of the first column and a top end of the third column and having a first channel structure between the second string select gate and the first column and a second channel structure between the second string select gate and the third column;

wherein the first string select gate is configured to couple the top end of the first column to the source line and to couple the top end of the second column to the data line when the first string select gate is activated; and

wherein the second string select gate is configured to couple the top end of the first column to the source line and to couple the top end of the third column to the data line when the second string select gate is activated.

17. The memory device of claim 16, further comprising:

control circuitry, wherein the control circuitry is configured to independently activate and deactivate the first and the second string select gates.

18. The memory device of claim 17, wherein the control circuitry is further configured to deactivate the first string select gate when the second string select gate is activated, and to deactivate the second string select gate when the first string select gate is activated.

19. The memory device of claim 17, further comprising a plane gate, wherein the first, second and third columns are vertically formed on the plane gate.

20. The memory device of claim 19, wherein the plane gate is configured to couple a bottom end of the first column to a bottom end of the second column, and to couple the bottom end of the first column to a bottom end of the third column, when the plane gate is activated.

21. The memory device of claim 20, wherein the control circuitry is further configured to activate the plane gate when either the first string select gate or the second string select gate is activated.

22. The memory device of claim 17, wherein the control circuitry is further configured to perform a memory device operation where the memory device operation is selected from a group consisting of a read operation, a write operation, and an erase operation.

23. A memory device, comprising:

a data line;

a first source line;

a second source line;

a first string of series coupled memory cells formed along a first side of a first column and along a side of a second column, where the side of the second column is adjacent to the first side of the first column;

a second string of series coupled memory cells formed along a second side of the first column and along a side of a third column, where the side of the third column is adjacent to the second side of the first column;

a first string select gate formed between a top end of the first column and a top end of the second column and having a first channel structure between the first string select gate and the first column and a second channel structure between the first string select gate and the second column; and

a second string select gate formed between a top end of the first column and a top end of the third column and having a first channel structure between the second string select gate and the first column and a second channel structure between the second string select gate and the third column;

wherein the first string select gate is configured to couple the top end of the first column to the data line and to couple the top end of the second column to the first source line when the first string select gate is activated; and

wherein the second string select gate is configured to couple the top end of the first column to the data line and to couple the top end of the third column to the second source line when the second string select gate is activated.

24. The memory device of claim 23, further comprising:

control circuitry, wherein the control circuitry is configured to independently activate and deactivate the first and the second string select gates.

25. A memory device, comprising:

a data line;

a source line;

a first column formed vertically on a semiconductor substrate, wherein the first column comprises a first string of serially-connected memory cells formed along a vertical wall of the first column;

a second column formed vertically on the semiconductor substrate, wherein the second column comprises a second string of serially-connected memory cells formed along a vertical wall of the second column adjacent to the first string of serially-connected memory cells; and

a string select gate, wherein the string select gate is formed between a top portion of the first column and a top portion of the second column and comprises a first channel structure between the string select gate and the first column and a second channel structure between the string select gate and the second column;

wherein the string select gate is configured to couple a top memory cell of first string to the data line and a top memory cell of the second string to the source line when the string select gate is activated.

26. The memory device of claim 25, wherein the string select gate is further configured to decouple the top memory cell of first string from the data line and to decouple the top memory cell of the second string from the source line when the string select gate is deactivated.

27. The memory device of claim 25, wherein a bottom memory cell of the first string of serially-connected memory cells is coupled to a bottom memory cell of the second string of serially-connected memory cells.

28. The memory device of claim 25, further comprising a control gate formed at least partially between the bottom memory cells of the first string and the second string of serially-connected memory cells.

29. The memory device of claim 28, wherein the control gate is configured to couple the bottom memory cells of the first string and the second string of serially-connected memory cells when the control gate is activated.

30. The memory device of claim 25, wherein the memory device further comprises one or more additional columns formed vertically on the semiconductor substrate, wherein the one or more additional columns each comprises a string of serially-connected memory cells formed along a vertical wall of the one or more additional columns.

31. The memory device of claim 30, wherein the memory device further comprises a plane gate formed under the first column, the second column and the one or more additional columns.

32. The memory device of claim 25, wherein the first string and the second string of serially-connected memory cells comprise a continuous channel structure formed between the top memory cell of the first string and the top memory cell of the second string of serially-connected memory cells.

33. The memory device of claim 32, wherein the first string and the second string of serially-connected memory cells further comprise a continuous charge storage structure formed between the top memory cell of the first string and the top memory cell of the second string of serially-connected memory cells.

34. The memory device of claim 32, wherein each memory cell of the first string and the second string of serially-connected memory cells each comprises an intergate dielectric layer, an isolated floating gate structure, and a tunnel dielectric layer.

35. A method of operating a memory device, the method comprising:

activating a string select gate to couple a first end of a string of serially-connected memory cells to a data line through a first channel structure of the string select gate and to couple a second end of the string of serially-connected memory cells to a source line through a second channel structure of the string select gate when one or more memory cells of the string is selected for a memory device operation; and

deactivating the string select gate to decouple the first end of the string of serially-connected memory cells from the data line and to decouple the second end of the string of serially-connected memory cells from the source line when no memory cell of the string of serially-connected memory cells is selected for a memory device operation.

36. The method of claim 35, wherein activating the string select gate when one or more memory cells of the string is selected for a memory device operation further comprises activating the string select gate when one or more memory cells of the string is selected for a memory device operation selected from the group consisting of a read operation, a write operation, and an erase operation.

37. A method of forming a string of serially-connected memory cells, the method comprising:

forming a first column and a second column over a semiconductor substrate, wherein the first and the second column each comprise alternating structures of dielectric and conductive material, and where the first and the second column are separated by a particular distance;

forming a continuous charge storage structure over the first and second columns and a region of the semiconductor substrate between the first and the second columns;

forming a continuous channel structure over the continuous charge storage structure; and

forming a string select gate structure between a top structure of the alternating structures of the first column and a top structure of the alternating structures of the second column, wherein the string select gate is formed to concurrently selectively provide conductivity to a portion of the continuous channel structure between the string select gate structure and the top structure of the alternating structures of the first column, and to a portion of the continuous channel structure between the string select gate structure and the top structure of the alternating structures of the second column.