Structure for flash memory cells

• US 8,445,953 B2
• Filed: 04/22/2010
• Issued: 05/21/2013
• Est. Priority Date: 07/08/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Shen, Ming-Hui, Liu, Shih-Chang, Lo, Chi-Hsin, Tsai, Chia-Shiung, Tsao, Tsun Kai
• Primary Examiner(s): Lee, Eugene
• Application Number:
  US12/765,658
• Publication Number:
  US 20110006355A1
• Time in Patent Office: 1,125 Days
• Field of Search: 257/314, 257/316
• US Class Current: 257/316
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A flash memory cell structure is provided. A semiconductor structure includes a semiconductor substrate, a floating gate overlying the semiconductor substrate, a word-line adjacent to the floating gate, an erase gate adjacent to a side of the floating gate opposite the word-line, a first sidewall disposed between the floating gate and the word-line, and a second sidewall disposed between the floating gate and the erase gate. The first sidewall has a first characteristic and the second sidewall has a second characteristic. The first characteristic is different from the second characteristic.

Claims

1. A semiconductor structure comprising:

a semiconductor substrate;

a floating gate overlying the semiconductor substrate;

a control gate disposed on the floating gate;

a word-line adjacent to the floating gate;

an erase gate adjacent to a side of the floating gate opposite the word-line;

a first spacer extending up a side of the floating gate and the control gate, the first spacer comprising a first plurality of first spacer layers disposed between the floating gate and the word line, and a second plurality of first spacer layers disposed between the control gate and the word line, wherein the first plurality of first spacer layers has fewer layers than the second plurality of first spacer layers; and

a second spacer disposed between the floating gate and the erase gate.

2. The semiconductor structure of claim 1, further comprising:

a separation layer disposed between the control gate and the floating gate.

3. The semiconductor structure of claim 1, wherein the first plurality of first spacer layers comprises:

a first oxide layer disposed between the floating gate and the word-line; and

a first isolation layer disposed between the word-line and the first oxide layer.

4. The semiconductor structure of claim 1, wherein the second spacer comprises a second oxide layer disposed between the floating gate and the erase gate.

5. The semiconductor structure of claim 1, wherein the first spacer is formed from materials different from materials used to form the second spacer.

6. The semiconductor structure of claim 1, wherein the first spacer is thicker than the second spacer.

7. The semiconductor structure of claim 1, further comprising:

a second floating gate disposed on the semiconductor substrate, the second floating gate disposed on a side of the erase gate opposite the floating gate;

a second control gate disposed on the second floating gate;

a second word-line disposed on the semiconductor substrate and adjacent to a side of the second floating gate and the second control gate opposite the erase gate; and

a third spacer comprising a first plurality of third spacer layers disposed between the second floating gate and the second word-line, and a second plurality of third spacer layers disposed between the second control gate and the word line, wherein the first plurality of third spacer layers has fewer layers than the second plurality of third spacer layers.

8. The semiconductor structure of claim 7, further comprising a fourth spacer disposed between the second floating gate and the erase gate.

9. The semiconductor structure of claim 8, wherein the fourth spacer is thinner than the third spacer.

10. The semiconductor structure of claim 3, wherein the second plurality of first spacer layers comprises:

the first oxide layer and the isolation layer disposed between the control gate and the word line; and

a second isolation layer disposed between the first oxide layer and the control gate.