Reverse leakage reduction and vertical height shrinking of diode with halo doping

• US 8,450,835 B2
• Filed: 04/29/2008
• Issued: 05/28/2013
• Est. Priority Date: 04/29/2008
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Chen, Xiying, Clark, Mark H., Herner, S. Brad, Kumar, Tanmay
• Primary Examiner(s): CHEN, JACK S J
• Application Number:
  US12/149,217
• Publication Number:
  US 20090268508A1
• Time in Patent Office: 1,855 Days
• Field of Search: 257/656, 257/104, 257/109, 257/110, 257/E21.459
• US Class Current: 257/656
• CPC Class Codes: H01L 29/1606 Graphene
• CPC Class Codes: H01L 29/8615 Hi-lo semiconductor devices, e.g. memory devices
• CPC Class Codes: H01L 29/868 PIN diodes

Abstract

One embodiment of the invention provides a semiconductor diode device including a first conductivity type region, a second conductivity type region, where the second conductivity type is different from the first conductivity type, an intrinsic region located between the first conductivity type region and the second conductivity type region; a first halo region of the first conductivity type located between the second conductivity type region and the intrinsic region, and optionally a second halo region of the second conductivity type located between the first conductivity type region and the intrinsic region.

Claims

1. A semiconductor diode device, comprising:

a first conductivity type region;

a second conductivity type region, wherein the second conductivity type is different from the first conductivity type;

an intrinsic region located between the first conductivity type region and the second conductivity type region;

a first halo region of the first conductivity type located between the second conductivity type region and the intrinsic region, the first halo region directly contacting the second conductivity region;

wherein the first conductivity type region and the second conductivity type region of the diode device have a thickness ranging from 5 angstroms to 1 micron;

wherein the first halo region has a thickness ranging from 10 angstroms to 3 microns,

wherein the semiconductor diode device is a two terminal device,

wherein the first conductivity type region, second conductivity type region, intrinsic region and first halo region have a cylindrical shape, and

wherein a doping concentration of the first conductivity type region and doping concentration of second conductivity type region are higher than 1×

10¹⁹ cm<sup>−

3</sup> and a doping concentration of the first halo region is higher than 1×

10¹⁷ cm<sup>−

3</sup> and lower than 1×

10¹⁹ cm<sup>−

3</sup>.

2. A device of claim 1, further comprising a second halo region of the second conductivity type located between the first conductivity type region and the intrinsic region.

3. A device of claim 1, wherein the first halo region is lightly doped, and wherein the first conductivity type region and the second conductivity type region are heavily doped.

4. A device of claim 1, wherein:

the first conductivity type region and the second conductivity type region have a thickness ranging from 200 angstroms to 500 angstroms;

the intrinsic region has a thickness ranging from 1500 angstroms to 2500 angstroms; and

the first halo region has a thickness ranging from 100 angstroms to 300 angstroms.

5. A device of claim 4, wherein:

the diode is selected from a group consisting of p⁺-n⁻

-i-n⁺ semiconductor diode, p⁺-i-p⁻

-n⁺ semiconductor diode, p⁺-n⁻

-i-p⁻

-n⁺ semiconductor diode, n⁺-i-n⁻

-p⁺ semiconductor diode, n⁺-p⁻

-i-p⁺ semiconductor diode, and n⁺-p⁻

-i-n⁻

-p⁺ semiconductor diode;

the first conductivity type region, first halo region, intrinsic region, and second conductivity type region of the diode are arranged vertically in series.

6. A nonvolatile memory device, comprising:

at least one memory cell which comprises a steering element and a storage element, wherein the steering element comprises the diode of claim 1; and

a first electrode and a second electrode electrically contacting the at least one memory cell.

7. A device of claim 6, wherein the memory cell type is selected from at least one of antifuse, fuse, diode and antifuse arranged in a series, polysilicon memory effect cell, metal oxide memory, switchable complex metal oxide, carbon nanotube memory, graphene switchable resistance material, phase change material memory, conductive bridge element, or switchable polymer memory.

8. A device of claim 6, wherein the storage element comprises a resistivity switching element.

9. A device of claim 8, wherein the resistivity switching element comprises a metal oxide antifuse dielectric layer.

10. A device of claim 9, wherein the diode and the metal oxide antifuse dielectric layer are arranged in series between the first and the second electrodes.

11. A device of claim 6, wherein the memory cell is a read/write memory cell or a rewritable memory cell.

12. A device of claim 6, wherein the nonvolatile memory device comprises a monolithic, three dimensional array of memory cells.