Device comprising a field-effect transistor in a silicon-on-insulator

• US 8,455,938 B2
• Filed: 09/20/2010
• Issued: 06/04/2013
• Est. Priority Date: 04/22/2010
• Status: Active Grant

• Current Assignee: Soitec S.A.
• Original Assignee: Soitec S.A.
• Inventors: Nguyen, Bich-Yen, Mazure, Carlos, Ferrant, Richard
• Primary Examiner(s): Malsawma, Lex
• Application Number:
  US12/886,421
• Publication Number:
  US 20110260233A1
• Time in Patent Office: 988 Days
• Field of Search: 257/347, 257/E29.265
• US Class Current: 257/316
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0705 comprising components of the field effect type
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence

Abstract

The present invention relates to a semiconductor device that has a semiconductor-on-insulator (SeOI) structure, which includes a substrate, an insulating layer such as an oxide layer on the substrate and a semiconductor layer on the insulating layer with a field-effect-transistor (FET) formed in the SeOI structure from the substrate and deposited layers, wherein the FET has a channel region in the substrate, a gate dielectric layer that is made from at least a part of the oxide layer of the SeOI structure; and a gate electrode that is formed at least partially from a part of the semiconductor layer of the SeOI structure. The invention further relates to a method of forming one or more field-effect-transistors or metal-oxide-semiconductor transistors from a semiconductor-on-insulator structure that involves patterning and etching the SeOI structure, forming shallow trench isolations, depositing insulating, metal or semiconductor layers, and removing mask and/or pattern layers.

Claims

1. A semiconductor device, comprising

a semiconductor-on-insulator (SeOI) structure, comprising:

a substrate;

an insulating layer on the substrate; and

a semiconductor layer on the insulating layer, wherein a first field-effect-transistor (FET) is formed therein, and further wherein the first FET comprises;

a channel region in the substrate;

a dielectric layer formed at least partially from a part of the insulating layer of the semiconductor-on-insulator structure; and

a gate formed at least partially from a first part of the semiconductor layer of the semiconductor-on-insulator structure; and

a second FET formed in the semiconductor-on-insulator structure, the structure comprising a channel region and source and drain regions made of a second part of the semiconductor layer of the semiconductor-on-insulator structure;

wherein the first part of the semiconductor layer of the SeOI structure and the second part of the semiconductor layer of the SeOI structure at least partially overlap each other.

2. The semiconductor device according to claim 1, wherein the semiconductor-on-insulator structure is a silicon-on-insulator (SOI) structure, wherein the semiconductor layer is a single crystal silicon layer and the insulating layer is an oxide.

3. The semiconductor device according to claim 1, wherein the insulating layer is an oxide that forms a buried oxide (BOX) layer in the semiconductor-on-insulator structure.

4. The semiconductor device according to claim 1, wherein the dielectric layer forms a gate dielectric of the FET, and the gate is a gate electrode that is further comprised of a layer of polysilicon on the first part of the semiconductor layer of the semiconductor-on-insulator structure.

5. The semiconductor device according to claim 1, wherein the first part of the semiconductor layer of the SeOI structure forms at least partially a source or drain region of the other FET.

6. The semiconductor device according to claim 1, which further comprises forming an additional FET comprising a channel region and source and drain regions from a third part of the semiconductor layer of the semiconductor-on-insulator structure.

7. The semiconductor device according to claim 6, wherein the first part of the semiconductor layer of the semiconductor-on-insulator structure is different from the third part of the semiconductor layer of the semiconductor-on-insulator structure;

and further comprising;

an insulator region, wherein the insulator region is a shallow trench isolation feature separating the FET comprising the dielectric that is made from a part of the insulating layer of the semiconductor-on-insulator structure from the additional FET.

8. The semiconductor device of claim 7, wherein the insulator region is a shallow trench isolation feature separating the FET made from part of the third part of the semiconductor layer from the FET made from the first part of the semiconductor layer.

9. A method for manufacturing a field effect transistor (FET) in a semiconductor device according to claim 1, which comprises:

forming the first FET by providing a semiconductor-on-insulator (SeOI) structure which comprises;

a substrate;

an insulating layer on the substrate; and

a semiconductor layer on the insulating layer; and

forming a polysilicon layer on the semiconductor layer to obtain a polysilicon on SeOI structure; and

etching the polysilicon on SeOI structure to form a FET comprising;

a channel region in the substrate;

a gate dielectric made from a first part of the insulating layer of the SeOI structure; and

a gate electrode at least partially made of a first part of the semiconductor layer of the SeOI structure and a part of the polysilicon layer formed on the semiconductor layer.

10. The method according to claim 9, which further comprises introducing dopants into the SeOI structure to create the channel region and a source and a drain region in the substrate.

11. The method according to claim 10, which further comprises manufacturing a floating gate FET and a MOSFET on the SeOI structure by:

forming a gate dielectric on the semiconductor layer of the SeOI structure;

forming a gate electrode on a first part of the gate dielectric, wherein at least a part of the semiconductor layer is a floating gate;

forming source and drain regions in the semiconductor layer, such that either one of the source or drain regions is at least partly formed of at least a part of the floating gate that is at least a part of the first part of the semiconductor layer of the SeOI structure;

forming a metal layer on a second part of the gate dielectric;

forming a polysilicon layer on the metal layer; and

etching the metal layer and polysilicon layer to form a MOSFET gate electrode on the second part of the gate dielectric.

12. The method according to claim 9, which further comprises:

manufacturing a MOSFET on the SeOI structure by;

forming a gate dielectric on the semiconductor layer of the SeOI structure, wherein the semiconductor layer is a single crystal silicon layer;

forming a gate electrode on the gate dielectric; and

forming source and drain regions such that one of the source and drain regions is at least partly formed of at least a part of the gate electrode that is at least partially made of the first part of the single crystal silicon layer of the SeOI structure

forming a metal layer on a second part of the gate dielectric;

forming a polysilicon layer on the metal layer; and

etching the metal layer and polysilicon layer to form a MOSFET gate electrode on the second part of the gate dielectric.

13. The method according to claim 9, which further comprises manufacturing a metal-oxide-semiconductor (MOSFET) in addition to a FET, by:

forming a mask layer on the SeOI structure;

forming a shallow trench isolation through the mask layer extending to the substrate and separating a first region of the SeOI structure from a second region of the SeOI structure;

removing the mask layer from the second region of the SeOI structure;

subsequently forming a dielectric layer on the second region of the SeOI structure;

forming a metal layer on the dielectric layer;

etching the metal layer, the dielectric layer and the SeOI structure in the second region to form a MOSFET in the second region of the SeOI structure; and

removing the mask layer from the first region of the SeOI structure;

wherein the polysilicon layer is formed on the semiconductor layer in the first region of the SeOI structure after removing the mask layer to obtain the polysilicon layer on SeOI structure and on the metal layer in the second region.

14. The method according to claim 9, wherein the providing of the SeOI structure comprises:

providing an silicon-on-insulator (SOI) stack comprising;

a substrate layer;

a first insulating layer on the substrate layer; and

a single crystal silicon layer on the first insulating layer;

forming an oxide layer on the single crystal silicon layer;

forming a mask layer on the oxide layer; and

patterning the oxide layer and the mask layer to form a structure wherein a first part of the single crystal silicon layer is exposed.

15. The method according to claim 14, which further comprises:

thermally oxidizing the structure and exposed single crystal silicon layer to form a silicon oxide layer on the previously exposed single crystal silicon layer and a first thinned single crystal silicon layer; and

removing the oxide layer and the mask layer and the silicon oxide layer formed on the previously exposed single crystal silicon layer;

wherein the first part of the single crystal silicon layer of the SOI structure is at least a part of the first thinned single crystal silicon layer.

16. The method according to claim 14, wherein the first insulating layer of the silicon-on-insulator (SOI) stack is a silicon dioxide layer, and which further comprises:

subjecting the structure and exposed single crystal silicon layer to an anneal process thereby partially dissolving the part of the silicon dioxide layer beneath the exposed first part of the single crystal silicon layer in order to obtain a thinned silicon dioxide layer; and

removing the second oxide layer on the single crystal silicon layer and the mask layer on the second oxide layer; and

wherein the part of the oxide layer of the SOI structure is at least a part of the thinned silicon dioxide layer.

17. The method of claim 16, wherein the semiconductor-on-insulator (SeOI) structure is a silicon-on-insulator (SOI) structure, further wherein the semiconductor layer is a single crystal silicon layer.

18. A semiconductor device comprising:

a semiconductor-on-insulator (SeOI) structure comprising;

a substrate;

an insulating layer on the substrate; and

a semiconductor layer on the insulating layer, wherein a field-effect-transistor (FET) is formed therein as a floating gate FET, and further wherein the FET comprises;

a channel region in the substrate;

a dielectric layer formed at least partially from a part of the insulating layer of the semiconductor-on-insulator structure;

a gate formed at least partially from a first part of the semiconductor layer of the semiconductor-on-insulator structure;

a tunnel dielectric formed at least partially from the insulating layer;

a floating gate above the tunnel dielectric and formed at least partially from the semiconductor layer;

a gate dielectric layer above the floating gate; and

a gate electrode formed above the gate dielectric, wherein the floating gate is separated from the gate electrode by the gate dielectric and from the channel region in the substrate by the tunnel dielectric.

19. A method for manufacturing a floating gate field effect transistor in a semiconductor device according to claim 18, which comprises:

providing a semiconductor-on-insulator (SeOI) structure comprising;

a substrate;

an insulating layer on the substrate; and

a semiconductor layer on the insulating layer;

forming a dielectric layer on the semiconductor layer;

forming a polysilicon layer on the dielectric layer to obtain a multilayer structure; and

etching the multilayer structure to form a floating-gate FET comprising;

a channel region in the substrate;

a tunnel dielectric made from a part of the insulating layer of the SeOI structure;

a floating gate made of a first part of the semiconductor layer of the SeOI structure;

a gate dielectric made of a part of the dielectric layer formed on the semiconductor layer; and

a gate electrode comprising a part of the polysilicon layer formed on the dielectric layer.

20. The method according to claim 19, which further comprises:

forming a mask layer on the SeOI structure;

forming a shallow trench isolation through the mask layer extending to the substrate and separating a first region of the SeOI structure from a second region of the SeOI structure;

removing the mask layer from the second region of the SeOI structure;

subsequently forming a second dielectric layer on the second region of the SeOI structure;

forming a metal layer on the second dielectric layer;

removing the mask layer from the first region of the SeOI structure; and

etching the metal layer, the second dielectric layer and the SeOI structure in the second region to form the MOSFET in the second region of the SeOI structure; and

wherein the dielectric layer is formed on the semiconductor layer and the polysilicon layer is formed on the dielectric layer to obtain a multilayer structure in the first region of the SeOI structure.