Driving circuit for an electric load and electric system comprising the circuit

• US 8,461,977 B2
• Filed: 07/27/2010
• Issued: 06/11/2013
• Est. Priority Date: 07/28/2009
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Amighini, Matteo, Poma, Alberto, Di Biase, Giuseppe, Poletto, Vanni
• Primary Examiner(s): Vu, Bao Q
• Application Number:
  US12/844,067
• Publication Number:
  US 20110025282A1
• Time in Patent Office: 1,050 Days
• Field of Search: 340/450.2, 340/450, 340/425, 340/435, 324/601
• US Class Current: 340/450.2
• CPC Class Codes: H02H 5/10 responsive to mechanical injury, e.g. rupture of line, breakage of earth connection
• CPC Class Codes: H02H 7/12 for static converters or rectifiers for discharge lamp power supplies using static converters H05B41/2851, H05B41/2921, H05B41/2981
• CPC Class Codes: H02M 3/1555 for the generation of a regulated current to a load whose impedance is substantially inductive
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators

Abstract

An electronic circuit includes a node coupled to a load to be driven, and a power device, which can be switched between activation and deactivation and coupled to the node. The circuit further includes a current generator having an output connected to the node and that can be enabled to generate current at least when the power device is deactivated. The circuit also includes a comparator for comparing an electric voltage of the node with a reference voltage and is configured to generate a comparison signal based thereon.

Claims

1. A driving circuit comprising:

a node configured to be coupled to a load;

a further node configured to be coupled to the load;

an H-bridge circuit switchable between an activation mode and a deactivation mode and comprising

a first transistor having a first terminal coupled to said node and to be coupled to the load,

a second transistor coupled in series with said first transistor and having a second terminal coupled to said node,

a third transistor having a third terminal coupled to said further node, and

a fourth transistor coupled in series with said third transistor and having a fourth terminal coupled to said further node;

a current generator having an output coupled to said node, said current generator being configured to be enabled to generate a current at least when said H-bridge circuit is deactivated; and

a comparator configured to compare a voltage of said node to a reference voltage and generate a comparison signal based thereon.

2. The driving circuit according to claim 1, further comprising an electronic device coupled to said node and configured to switch between a conduction mode and an interdiction mode based upon transitions of the load between correct connection conditions and incorrect connection conditions.

3. The driving circuit according to claim 2, wherein said electronic device comprises a diode being configured to allow flowing of an electric current when the load is correctly connected and interrupt flowing of the electrical current when the load is incorrectly connected;

the voltage of said node varying with transitions of the load between correct connection conditions and incorrect connection conditions.

4. The driving circuit according to claim 1, wherein said current generator is configured to be disabled in a condition of correct connection of the load and configured to be enabled to generate current in a condition of incorrect connection of the load.

5. The driving circuit according to claim 1, wherein said current generator is configured to provide an electric current equal to a current that places the load in a reference condition corresponding to the load being incorrectly connected to said node.

6. The driving circuit according to claim 5, wherein said current generator comprises a control terminal to receive a control digital signal to switch the current generator between current generation enabling and current generation disabling modes.

7. The driving circuit according to claim 1, further comprising a driving controller configured to generate a driving voltage for said power device;

and wherein said power device comprises a power transistor having a control terminal coupled to said driving controller.

8. The driving circuit according to claim 1, further comprising an electronic device coupled to said node and configured to switch between a conduction mode and an interdiction mode based upon transitions of the load between correct connection conditions and incorrect connection conditions;

and wherein said electronic device comprises a parasitic diode coupled to said second transistor.

9. The driving circuit according to claim 7, wherein said driving controller is configured to generate the driving voltage in accordance with a pulse width modulation (PWM) technique based on a driving enabling signal.

10. The driving circuit according to claim 9, further comprising:

a sequential logic device configured to receive the comparison signal and combine it with the driving enabling signal to obtain a detection signal;

a synchronous memory device configured to acquire and transmit on a respective output, a logical level assumed by the detection signal; and

a logic block configured to command the acquisition and the transmission of the logical level by said synchronous memory device.

11. The driving circuit according to claim 10, wherein said logic block is further configured to:

evaluate a first duty cycle assigned to the driving enabling signal; and

assign to the driving enabling signal, a second duty cycle lower than the first duty cycle if the first duty cycle is equal to 100%.

12. An electrical system comprising:

a load;

a driving circuit coupled to said load and comprising

a node coupled to said load,

a further node coupled to said load;

an H-bridge circuit switchable between an activation mode and a deactivation mode and comprising

a first transistor having a first terminal coupled to said node and said load,

a second transistor coupled in series with said first transistor and having a second terminal coupled to said node,

a third transistor having a third terminal coupled to a further node, and

a fourth transistor coupled in series with said third transistor and having a fourth terminal coupled to said further node,

a current generator having an output coupled to said node, said current generator being configured to be enabled to generate a current at least when said H-bridge circuit is deactivated, and

a comparator configured to compare a voltage of said node to a reference voltage and generate a comparison signal based thereon.

13. The electrical system according to claim 12, wherein said load comprises a coil.

14. The electrical system according to claim 13, further comprising:

a battery; and

an alternator configured to charge said battery;

said alternator comprising a rotor coupled to said coil.

15. The electrical system according to claim 14, further comprising:

a management block coupled to said driving circuit and configured to generate a command signal based upon a detection of an anomalous connection condition of said load; and

a signalling device configured to indicate an anomaly based upon the command signal.

16. A method of using a driving circuit comprising:

enabling a current generator to generate a current at an output coupled to a node when an H-bridge circuit switchable between an activation mode and a deactivation mode is deactivated, the H-bridge circuit comprising

a first transistor having a first terminal coupled to the node and a load,

a second transistor coupled in series with the first transistor and having a second terminal coupled to the node,

a third transistor having a third terminal coupled to a further node to be coupled to the load, and

a fourth transistor coupled in series with the third transistor and having a fourth terminal coupled to the further node;

comparing a voltage at the node to a reference voltage; and

generating a comparison signal based upon the comparison.

17. The method according to claim 16, further comprising configuring an electronic device coupled to the node to switch between a conduction mode and an interdiction mode based upon transitions of the load between correct connection conditions and incorrect connection conditions.

18. The method according to claim 17, wherein configuring the electronic device comprises configuring a diode coupled to the node to allow flowing of an electric current when the load is correctly connected and interrupt flowing of the electrical current when the load is incorrectly connected.

19. A driving circuit comprising:

a node configured to be coupled to a load to be driven;

a power device switchable between an activation mode and a deactivation mode and coupled to said node, said power device comprising a power transistor having a control terminal;

a current generator having an output coupled to said node, said current generator being configured to be enabled to generate a current at least when said power device is deactivated;

a comparator configured to compare a voltage of said node to a reference voltage and generate a comparison signal based thereon; and

a driving controller coupled to said control terminal and configured to generate a driving voltage for said power device in accordance with a pulse width modulation (PWM) technique based on a driving enabling signal.

20. The driving circuit according to claim 19, further comprising an electronic device coupled to said node and configured to switch between a conduction mode and an interdiction mode based upon transitions of the load between correct connection conditions and incorrect connection conditions.

21. The driving circuit according to claim 20, wherein said electronic device comprises a diode being configured to allow flowing of an electric current when the load is correctly connected and interrupt flowing of the electrical current when the load is incorrectly connected;

the voltage of said node varying with transitions of the load between correct connection conditions and incorrect connection conditions.

22. The driving circuit according to claim 19, wherein said current generator is configured to be disabled in a condition of correct connection of the load and configured to be enabled to generate current in a condition of incorrect connection of the load.

23. The driving circuit according to claim 19, wherein said current generator is configured to provide an electric current equal to a current that places the load in a reference condition corresponding to the load being incorrectly connected to said node.

24. The driving circuit according to claim 23, wherein said current generator comprises a control terminal to receive a control digital signal to switch the current generator between current generation enabling and current generation disabling modes.

25. The driving circuit according to claim 19, wherein said power device comprises an H-bridge circuit comprising:

a first transistor including a first terminal coupled to said node and configured to be coupled to a first driving terminal of the load;

a second transistor coupled in series with said first transistor and having a second terminal coupled to said node;

a third transistor having a third terminal coupled to a further node, the further node being configured to be coupled to a second supplying node of the load; and

a fourth transistor coupled in series with said third transistor and having a fourth terminal coupled to said further node.

26. The driving circuit according to claim 25, further comprising an electronic device coupled to said node and configured to switch between a conduction mode and an interdiction mode based upon transitions of the load between correct connection conditions and incorrect connection conditions;

and wherein said electronic device comprises a parasitic diode coupled to said second transistor.

27. The driving circuit according to claim 19, further comprising:

a sequential logic device configured to receive the comparison signal and combine it with the driving enabling signal to obtain a detection signal;

a synchronous memory device configured to acquire and transmit on a respective output, a logical level assumed by the detection signal; and

a logic block configured to command the acquisition and the transmission of the logical level by said synchronous memory device.

28. The driving circuit according to claim 27, wherein said logic block is further configured to:

evaluate a first duty cycle assigned to the driving enabling signal; and

assign to the driving enabling signal, a second duty cycle lower than the first duty cycle if the first duty cycle is equal to 100%.

29. A method of using a driving circuit comprising:

enabling a current generator to generate a current at a node when a power device switchable between an activation mode and a deactivation mode is deactivated, the power device comprising a power transistor having a control terminal;

comparing a voltage at the node to a reference voltage;

generating a comparison signal based upon the comparison; and

generating a driving voltage for the power device using a driving controller coupled to the control terminal, the driving voltage being generated in accordance with a pulse width modulation (PWM) technique based on a driving enabling signal.

30. The method according to claim 29, further comprising configuring an electronic device coupled to the node to switch between a conduction mode and an interdiction mode based upon transitions of the load between correct connection conditions and incorrect connection conditions.

31. The method according to claim 30, wherein configuring the electronic device comprises configuring a diode coupled to the node to allow flowing of an electric current when the load is correctly connected and interrupt flowing of the electrical current when the load is incorrectly connected.

32. The method according to claim 29, wherein the power device comprises an H-bridge circuit comprising:

a first transistor coupled to the node and configured to be coupled to the load;

a second transistor coupled in series with the first transistor and coupled to the node;

a third transistor coupled to a further node, the further node being configured to be coupled to a second supplying node of the load; and

a fourth transistor coupled in series with the third transistor and coupled to the further node.