Programmable semiconductor interposer for electronic package and method of forming

• US 8,476,735 B2
• Filed: 05/29/2007
• Issued: 07/02/2013
• Est. Priority Date: 05/29/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsu, Chao-Shun, Chao, Clinton, Peng, Mark Shane
• Primary Examiner(s): Gurley, Lynne
• Assistant Examiner(s): YUSHINA, GALINA G
• Application Number:
  US11/807,505
• Publication Number:
  US 20080296697A1
• Time in Patent Office: 2,226 Days
• Field of Search: 257/379, 257/433, 257678-733, 257/776, 257/390, 257/370, 257/E27.076, 257/E27.009, 257/499, 257/516, 257528-533, 250/208.1, 361/806, 361/762, 716/16
• US Class Current: 257/528
• CPC Class Codes: H01L 21/76886 Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5382 Adaptable interconnections, e.g. for engineering changes
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/157 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2924/19011 : including integrated passive components

Abstract

Various structures of a programmable semiconductor interposer for electronic packaging are described. An array of semiconductor devices having various values is formed in the interposer. A user can program the interposer and form a “virtual” device having a desired value by selectively connecting various one of the array of devices to contact pads formed on the surface of the interposer. An inventive electronic package structure includes a standard interposer having an array of unconnected devices of various values and a device selection unit, which selectively connects various one of the array of devices in the standard interposer to an integrated circuit die encapsulated in the electronic package. Methods of forming the programmable semiconductor interposer and the electronic package are also illustrated.

Claims

1. A semiconductor interposer comprising:

a semiconductor substrate;

an array of passive devices having various electrical parameters formed in an insulating material on said substrate, said passive devices being connected to vertical interconnects extending to an intermediate interface at the surface of said insulating material;

said array of passive devices being arranged in two or more vertical layers within the insulating material and at least one of said passive devices having portions overlying other portions of said passive devices separated by said insulating material;

one or more first conductive contact pads formed on a first surface of said interposer;

one or more second conductive contact pads formed on a second surface of said interposer;

one or more conductive paths passing through said interposer and connecting at least one of the first conductive contact pads to at least one of the second conductive contact pads wherein the one or more conductive paths are not physically connected to any one of the array of passive devices;

a device selection unit formed over the insulating material, wherein said device selection unit selectively connects at least one of said passive semiconductor devices to said first conductive contact pads, wherein electrical connectors of the device selection unit are surrounded by at least one dielectric material, and wherein said device selection unit selectively serially connects the vertical interconnect of said at least one of said passive devices to the vertical interconnect of another at least one of said passive devices such that an integrated device attached to said interposer has a desired electrical parameter for the integrated device.

2. The interposer of claim 1 wherein said semiconductor substrate comprises a silicon layer.

3. The interposer of claim 1 wherein said array of passive devices comprises a resistor, a capacitor, an inductor, a transmission line, a fuse, an antifuse, or a MEMS.

4. The interposer of claim 1 wherein said device selection unit is a custom conductive layer formed on said insulating material.

5. The interposer of claim 1 wherein said device selection unit is an interconnect matrix having at least two conductive layers formed in a top portion of another insulating material, the at least two conductive layers arranged overlying one another and wherein a one-time programmable fuse or an antifuse is placed at each region of overlap of said at least two conductive layers.

6. The interposer of claim 1 wherein said device selection unit comprises a programmable logic circuitry that may read an external instruction and configure connections between said passive devices.

7. The interposer of claim 1, wherein at least one of said passive devices is not selected by the device selection unit and remains unconnected to any of the first or the second conductive pads.

8. The interposer of claim 1, wherein said device selection unit selectively connects at least two of said passive devices in parallel to form the device having a desired electrical parameter.

9. The interposer of claim 1, further comprising an array of another devices having various electrical parameters formed in said insulating material, wherein all the devices in the array of another devices are a same second type of device, the array of passive devices being different than the second type of devices, wherein said device selection unit selectively connects at least one of said another semiconductor devices to said first conductive contact pads.

10. The interposer of claim 9, wherein said device selection unit selectively connects at least two of said another devices to form a second device having another desired electrical parameter.

11. A semiconductor interposer comprising:

a semiconductor substrate;

an array of passive devices, which have various electrical parameters, being formed in at least two layers in an insulating material on said semiconductor substrate, the array of passive devices having vertical interconnects extending to an intermediate interface at the surface of said insulating material;

said array of passive devices being arranged in vertical layers and having portions overlying other portions of the passive devices separated by said insulating material;

one or more first conductive contact pads formed on a first surface of said interposer;

one or more second conductive contact pads formed on a second surface of said interposer;

one or more conductive paths passing through said interposer and connecting at least one of the first conductive contact pads to at least one of the second conductive contact pads, wherein the one or more conductive paths are not physically connected to any one of the array of passive devices;

wherein said passive devices can be selectively connected to each other by selectively coupling the vertical interconnects at the intermediate interface by forming connections overlying the insulating material, the connections being surrounded by at least one dielectric material, to form a device having a desired electrical parameter and be connected to said first conductive contact pads, and wherein at least one of said array of passive devices is not selected and remains unconnected to any of the first or the second conductive pads, such that said interposer presents a desired electrical parameter for the integrated device attached to the interposer.

12. The interposer of claim 11 wherein said semiconductor substrate comprises a silicon layer.

13. The interposer of claim 11 wherein said array of passive devices comprise at least a resistor, a capacitor, an inductor, a transmission line, a fuse, an antifuse, or a MEMS.

14. The interposer of claim 11, wherein all the devices in the array of passive devices are a same type of device.

15. The interposer of claim 11 wherein said selective connection between said passive devices are conducted by a device selection unit overlying the insulating material and selectively coupled to the vertical interconnects of respective ones of the passive devices, the connections of the device selection unit being surrounded by said at least one dielectric layer.

16. The interposer of claim 15 wherein said device selection unit is a custom conductive layer formed on said substrate.

17. The interposer of claim 15 wherein said device selection unit is an interconnect matrix having at least two conductive layers arranged one overlying the other and formed in a top portion of another insulating material, wherein a one-time programmable fuse or an antifuse is placed at each region of overlap of said at least two conductive layers.

18. An electronic package comprising:

at least one semiconductor interposer which includes a substrate, one or more first conductive contact pads formed on a first surface of said interposer, one or more second conductive contact pads formed on a second surface of said interposer, one or more conductive paths passing through said interposer and connecting at least one of the first conductive contact pads to at least one of the second conductive contact pads, an array of passive devices having various electrical parameters formed in and surrounded by an insulating material on said substrate, the array of passive devices being arranged in at least two vertical layers within said insulating material and at least one of the passive semiconductor devices having portions overlying other portions of the passive devices separated by said insulating material, wherein said passive devices have vertical interconnects extending to an interface layer and can be selectively connected to each other using the vertical interconnects by forming connections overlying the insulating material and surrounded by at least one dielectric layer in response to an applied voltage and said passive devices can be connected to said first conductive contact pads and form a device having a desired electrical parameter and wherein the one or more conductive paths are not physically connected to any one of the said array of passive devices; and

at least one semiconductor integrated circuit die electrically coupled to the at least one semiconductor interposer.

19. The electronic package of claim 18 wherein said selective connection between said passive devices is conducted by a device selection unit overlying the insulating material and selectively coupling respective ones of the vertical interconnects using connectors surrounded by said at least one dielectric layer.

20. A reconfigurable interposer for an integrated circuit die, comprising:

a substrate;

an array of passive devices having various electrical parameters formed in an insulating material on said substrate, said passive devices being connected to vertical interconnects extending to an intermediate interface at the surface of said insulating material;

said standard array of passive devices being arranged in two or more vertical layers within the insulating material and at least one of said passive semiconductor devices having portions overlying other portions of said passive devices separated by said insulating material;

a device selection unit for the integrated circuit die, wherein the device selection unit is formed over the insulating material, wherein said device selection unit selectively connects at least one of said passive devices to said first conductive contact pads, wherein electrical connectors of the device selection unit are surrounded by at least one dielectric material, and wherein said device selection unit selectively serially connects the vertical interconnect of said at least one of said passive devices to the vertical interconnect of another at least one of said passive devices to form the reconfigurable interposer for the integrated circuit die, wherein the reconfigurable interposer forms desired circuit functions complimentary to the integrated circuit die.