High speed processing of financial information using FPGA devices

  • US 8,478,680 B2
  • Filed: 03/31/2011
  • Issued: 07/02/2013
  • Est. Priority Date: 06/19/2006
  • Status: Active Grant
First Claim
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1. An apparatus comprising:

  • a reconfigurable logic device having firmware logic deployed thereon for processing a plurality of streaming financial market data order messages, each order message corresponding to a financial instrument and comprising (1) a symbol string for identifying the order message'"'"'s corresponding financial instrument and (2) financial market data that is representative of an offer to buy or sell its corresponding financial instrument, the firmware logic comprising a processing pipeline, the processing pipeline comprising a symbol mapping firmware application module (FAM) and an order book cache (OBC) FAM that is downstream from the symbol mapping FAM; and

    a memory configured to cache a plurality of financial instrument records, each financial instrument record corresponding to a financial instrument and comprising an order book for its corresponding financial instrument;

    wherein the symbol mapping FAM is configured to (1) receive the symbol strings for a plurality of the order messages, and (2) map the received symbol strings to a plurality of record keys for use by the OBC FAM to facilitate retrieval from the memory of the cached financial instrument records which correspond to the same financial instruments identified by the symbol strings;

    wherein the OBC FAM is configured to (1) receive streaming financial market data for a plurality of the order messages in association with the mapped record keys for those order messages, (2) retrieve the cached financial instrument records from the memory based on the record keys, (3) generate a plurality of updates for the financial instrument order books of the retrieved financial instrument records based on the received financial market data, and (4) update the cached financial instrument records in the memory based on the generated updates; and

    wherein the symbol mapping FAM and the OBC FAM are configured to operate simultaneously with respect to each other in a pipelined fashion such that the symbol mapping FAM is configured to operate with respect to an order message while the OBC FAM operates with respect to another order message.

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