Semiconductor memory device and method for driving the same

• US 8,482,974 B2
• Filed: 02/07/2011
• Issued: 07/09/2013
• Est. Priority Date: 02/12/2010
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Saito, Toshihiko, Matsuzaki, Takanori, Nagatsuka, Shuhei, Inoue, Hiroki
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US13/022,292
• Publication Number:
  US 20110199807A1
• Time in Patent Office: 883 Days
• Field of Search: 365/177, 365/189.14, 365/149, 365/77, 365/189.141
• US Class Current: 365/177
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A semiconductor device includes a first signal line, a second signal line, a memory cell, and a potential converter circuit. The memory cell includes a first transistor including a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region; a second transistor including a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region; and a capacitor. The first channel formation region and the second channel formation region include different semiconductor materials. The second drain electrode, one electrode of the capacitor, and the first gate electrode are electrically connected to one another. The second gate electrode is electrically connected to the potential converter circuit through the second signal line.

Claims

1. A semiconductor device comprising:

a first signal line;

a second signal line;

a memory cell; and

a circuit,

wherein the memory cell comprises;

a first transistor comprising a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region including a first semiconductor;

a second transistor comprising a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region including a second semiconductor; and

a first capacitor,

wherein the first semiconductor is different from the second semiconductor,

wherein the second drain electrode, an electrode of the first capacitor, and the first gate electrode are electrically connected to one another,

wherein the second gate electrode is electrically connected to the circuit through the second signal line,

wherein the second source electrode is electrically connected to the first signal line,

and

wherein the circuit is configured to output a second potential higher than a first potential to the second signal line in a case where the first potential is input to the circuit.

2. The semiconductor device according to claim 1, wherein the second semiconductor is an oxide semiconductor.

3. The semiconductor device according to claim 1,

wherein the circuit comprises:

a first wiring;

a second wiring;

a third wiring;

a third transistor comprising a third gate electrode, a third source electrode, a third drain electrode, and a third channel formation region including a third semiconductor;

a fourth transistor comprising a fourth gate electrode, a fourth source electrode, a fourth drain electrode, and a fourth channel formation region including a fourth semiconductor; and

a second capacitor,

wherein the second signal line, a first electrode of the second capacitor, and one of the fourth source electrode and the fourth drain electrode are electrically connected to one another,

wherein a second electrode of the second capacitor and one of the third source electrode and the third drain electrode are electrically connected to each other,

wherein the other one of the third source electrode and the third drain electrode and the first wiring are electrically connected to each other,

wherein the third gate electrode, the other one of the fourth source electrode and the fourth drain electrode, and the second wiring are directly connected to one another,

wherein the fourth gate electrode and the third wiring are electrically connected to each other,

wherein the first wiring is provided so as to be supplied with a power supply potential, and

wherein the second wiring is provided so as to be supplied with a power supply potential.

4. The semiconductor device according to claim 3, wherein the third semiconductor and the fourth semiconductor are each different from the second semiconductor.

5. The semiconductor device according to claim 3, wherein the third semiconductor and the fourth semiconductor are each an oxide semiconductor.

6. The semiconductor device according to claim 3,

wherein the circuit further comprises:

a fifth transistor comprising a fifth gate electrode, a fifth source electrode, a fifth drain electrode, and a fifth channel formation region; and

a fourth wiring,

wherein one of the fifth source electrode and the fifth drain electrode and the second signal line are electrically connected to each other,

wherein the other one of the fifth source electrode and the fifth drain electrode is grounded, and

wherein the fifth gate electrode and the fourth wiring are electrically connected to each other.

7. The semiconductor device according to claim 2, wherein the oxide semiconductor is an In—

Ga—

Zn—

O based oxide semiconductor.

8. The semiconductor device according to claim 1, wherein a capacitance of the first capacitor is larger than or equal to a capacitance of the first transistor.

25. The semiconductor device according to claim 1,

wherein the circuit is configured to output a low potential to the second signal line in a case where the low potential is input to the circuit, and

wherein the first potential is a high potential.

9. A semiconductor device comprising:

a first signal line;

a second signal line;

a source line;

a word line;

a bit line;

a memory cell; and

a circuit,

wherein the memory cell comprises;

a first transistor comprising a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region including a first semiconductor;

a second transistor comprising a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region including a second semiconductor; and

a first capacitor,

wherein the first semiconductor is different from the second semiconductor,

wherein the second drain electrode, one electrode of the first capacitor, and the first gate electrode are electrically connected to one another,

wherein the second gate electrode is electrically connected to the circuit through the second signal line,

wherein the second source electrode is electrically connected to the first signal line,

wherein the other electrode of the first capacitor is electrically connected to the word line,

wherein the first source electrode is electrically connected to the source line,

wherein the first drain electrode is electrically connected to the bit line, and

wherein the circuit is configured to output a second potential higher than a first potential to the second signal line in a case where the first potential is input to the circuit.

10. The semiconductor device according to claim 9, wherein the second semiconductor is an oxide semiconductor.

11. The semiconductor device according to claim 9,

wherein the circuit comprises:

a first wiring;

a second wiring;

a third wiring;

a third transistor comprising a third gate electrode, a third source electrode, a third drain electrode, and a third channel formation region including a third semiconductor;

a fourth transistor comprising a fourth gate electrode, a fourth source electrode, a fourth drain electrode, and a fourth channel formation region including a fourth semiconductor; and

a second capacitor,

wherein the second signal line, a first electrode of the second capacitor, and one of the fourth source electrode and the fourth drain electrode are electrically connected to one another,

wherein a second electrode of the second capacitor and one of the third source electrode and the third drain electrode are electrically connected to each other,

wherein the other one of the third source electrode and the third drain electrode and the first wiring are electrically connected to each other,

wherein the third gate electrode, the other one of the fourth source electrode and the fourth drain electrode, and the second wiring are directly connected to one another,

wherein the fourth gate electrode and the third wiring are electrically connected to each other,

wherein the first wiring is provided so as to be supplied with a power supply potential, and

wherein the second wiring is provided so as to be supplied with a power supply potential.

12. The semiconductor device according to claim 11, wherein the third semiconductor and the fourth semiconductor are each different from the second semiconductor.

13. The semiconductor device according to claim 11, wherein the third semiconductor and the fourth semiconductor are each an oxide semiconductor.

14. The semiconductor device according to claim 11,

wherein the circuit further comprises:

a fifth transistor comprising a fifth gate electrode, a fifth source electrode, a fifth drain electrode, and a fifth channel formation region; and

a fourth wiring,

wherein one of the fifth source electrode and the fifth drain electrode and the second signal line are electrically connected to each other,

wherein the other one of the fifth source electrode and the fifth drain electrode is grounded, and

wherein the fifth gate electrode and the fourth wiring are electrically connected to each other.

15. The semiconductor device according to claim 10, wherein the oxide semiconductor is an In—

Ga—

Zn—

O based oxide semiconductor.

16. The semiconductor device according to claim 9, wherein a capacitance of the first capacitor is larger than or equal to a capacitance of the first transistor.

26. The semiconductor device according to claim 9,

wherein the circuit is configured to output a low potential to the second signal line in a case where the low potential is input to the circuit, and

wherein the first potential is a high potential.

17. A semiconductor device comprising:

a signal line;

a memory cell; and

a circuit,

wherein the memory cell comprises;

a first transistor;

a second transistor comprising a channel formation region including an oxide semiconductor; and

a first capacitor,

wherein a first terminal of the second transistor, a terminal of the first capacitor, and a gate terminal of the first transistor are electrically connected to one another, and

wherein a gate terminal of the second transistor is electrically connected to the signal line, and

wherein the circuit comprises;

a first wiring;

a third transistor, wherein a first terminal of the third transistor is electrically connected to the first wiring;

a second capacitor, wherein a first terminal of the second capacitor, a second terminal of the third transistor, and the signal line are electrically connected to one another;

a fourth transistor, wherein a first terminal of the fourth transistor is electrically connected to a second terminal of the second capacitor; and

a second wiring electrically connected to a second terminal of the fourth transistor,

wherein a gate terminal of the fourth transistor is directly connected to the first wiring,

wherein the first wiring is provided so as to be supplied with a power supply potential, and

wherein the second wiring is provided so as to be supplied with a power supply potential.

18. The semiconductor device according to claim 17,

wherein the circuit further comprises a fifth transistor, and

wherein a first terminal of the fifth transistor is electrically connected to the signal line.

19. The semiconductor device according to claim 17, wherein a gate terminal of the fourth transistor is electrically connected to the first wiring.

20. The semiconductor device according to claim 17, wherein the oxide semiconductor is an In—

Ga—

Zn—

O based oxide semiconductor.

21. The semiconductor device according to claim 17, wherein the first terminal of the third transistor is electrically connected to a gate terminal of the fourth transistor.

22. The semiconductor device according to claim 17, wherein a capacitance of the first capacitor is larger than or equal to a capacitance of the first transistor.

23. A method for driving a semiconductor device, comprising:

selecting an on state or an off state of a second transistor to hold charge in a node where a gate electrode of a first transistor, one of a source electrode and a drain electrode of the second transistor, and an electrode of a first capacitor are electrically connected to one another,

wherein in a case where a potential is supplied to the node, a potential supplied to a gate electrode of the second transistor is higher than a power supply potential,

wherein the second transistor comprises a channel formation region including an oxide semiconductor,

wherein a method for supplying the potential supplied to the gate electrode of the second transistor through a first line comprises;

a first period where a potential, configured to make a fourth transistor an on state, is applied to a gate electrode of the fourth transistor; and

a second period where a potential, configured to make the fourth transistor an off state, is applied to the gate electrode of the fourth transistor and a potential is applied to a second line electrically connected to one of a source electrode and a drain electrode of a third transistor so as to bootstrap a potential of the first line after the first period,

wherein one of a source electrode and a drain electrode of the forth transistor and a first electrode of a second capacitor are electrically connected to the first line,

wherein a second electrode of the second capacitor is electrically connected to the other of the source electrode and the drain electrode of the third transistor, and

wherein the other of the source electrode and the drain electrode of the fourth transistor is directly connected to a gate electrode of the third transistor.

24. The method for driving a semiconductor device according to claim 23, wherein the potential supplied to the gate electrode of the second transistor is higher than a potential which is obtained by addition of a threshold voltage of the second transistor to the power supply potential.

27. The method for driving a semiconductor device according to claim 23, wherein the potential supplied to the node is a high potential.