Memory system

• US 8,484,432 B2
• Filed: 03/10/2009
• Issued: 07/09/2013
• Est. Priority Date: 03/11/2008
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hatsuda, Kosuke, Takashima, Daisaburo, Nagadomi, Yasushi
• Primary Examiner(s): Dudek, Jr., Edward
• Assistant Examiner(s): Rossiter, Sean D
• Application Number:
  US12/401,130
• Publication Number:
  US 20090235015A1
• Time in Patent Office: 1,582 Days
• Field of Search: 711/103, 711/170
• US Class Current: 711/173
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/2022 Flash memory

Abstract

A memory system includes a non-volatile memory constituted by blocks each of which is an erase unit constituted by pages each of which is a write/read unit constituted by memory cells; a random access memory temporarily storing data which is written in or read from the non-volatile memory; and a controller controlling the non-volatile memory and the random access memory, wherein the non-volatile memory includes a main memory area in which the block is divided into first management units respectively specified by logical addresses and a cache area in which the block is divided into second management units respectively specified by logical addresses, a data capacity of one of the second management units is smaller than that of one of the first management units, and the controller changes number of the blocks in the main memory area and number of the blocks in the cache area in the non-volatile memory.

Claims

1. A memory system comprising:

a non-volatile memory including a plurality of blocks, each one of the plurality of blocks being a data erase unit; and

a controller configured to assign one part of the plurality of blocks to a main memory area and to assign another part of the plurality of blocks to a cache area, wherein

each block is divided into multiple management units,

a plurality of data stored in the main memory area are managed with logical addresses, each logical address representing a first management unit,

a plurality of data stored in the cache area are managed with logical addresses, each logical address representing a second management unit,

the size of each second management unit is smaller than the size of each first management unit and the size of each of the first and second management units is smaller than the size of the data erase unit, and

the controller dynamically changes the number of the blocks assigned to the main memory area and the number of the blocks assigned to the cache area in the non-volatile memory.

2. The memory system according to claim 1, wherein the controller reduces the number of the blocks assigned to the cache area and increases the number of blocks assigned to the main memory area when an amount of data stored in the main memory area is larger than a predetermined value.

3. The memory system according to claim 1, wherein the controller determines whether data to be written that is received from outside of the non-volatile memory is stored in the main memory area or the cache area on the basis of the amount of the data to be written.

4. The memory system according to claim 2, wherein the controller determines whether data to be written that is received from outside of the non-volatile memory is stored in the main memory area or the cache area on the basis of the capacity of the data to be written.

5. The memory system according to claim 1, wherein the cache area stores data that has with higher access probability as compared to data stored in the main memory area.

6. The memory system according to claim 2, wherein the cache area stores data that has with higher access probability as compared to data stored in the main memory area.

7. The memory system according to claim 3, wherein the cache area stores data that has with higher access probability as compared to data stored in the main memory area.

8. The memory system according to claim 2, wherein

the controller searches for a first logical address from among logical addresses aligned by the second management unit to store data received from outside of the non-volatile memory in the cache area, and

when the amount of data stored in the main memory area is larger than a predetermined value, the controller reduces number of logical addresses to be searched so as to reduce the number of the blocks assigned to the cache area and increase the number of the blocks assigned to the main memory area.

9. The memory system according to claim 2, wherein the controller increases the number of the blocks assigned to the cache area and decreases the number of blocks assigned to the main memory area when an amount of data stored in the main memory area is smaller than the predetermined value.

10. The memory system according to claim 1, wherein the controller determines whether the cache area is full, and when the cache area is full, the controller copies data in the cache area to the main memory area.

11. The memory system according to claim 2, wherein when the cache area is full, the controller copies data in the cache area to the main memory area.

12. The memory system according to claim 11, wherein when an amount of data stored in the main memory area is larger than the predetermined value and the cache area is full, the controller copies valid data in one block to the other block in the main memory area and erases data in the one block.

13. The memory system according to claim 1, further comprising a random access memory temporarily storing data which is written in, or read from, the nonvolatile memory.

14. The memory system according to claim 1, wherein the non-volatile memory is a NAND type flash memory.