Method and apparatus for time-differential comparison of an analog signal

• US 8,497,729 B2
• Filed: 10/30/2012
• Issued: 07/30/2013
• Est. Priority Date: 12/21/2007
• Status: Expired due to Fees

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Polivka, William M.
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Cole, Brandon S
• Application Number:
  US13/664,213
• Publication Number:
  US 20130057316A1
• Time in Patent Office: 273 Days
• Field of Search: 327/115, 327/116, 327/117, 327/118, 327/199, 327355-360, 327/202, 327/203, 327208-215, 327/218, 377/47, 377/48
• US Class Current: 327/428
• CPC Class Codes: G01R 19/12 Measuring rate of change
• CPC Class Codes: H03K 5/24 the characteristic being amplitude
• CPC Class Codes: H03M 1/60 with intermediate conversion to frequency of pulses

Abstract

A time-differential analog comparator includes a variable frequency signal source, a timing circuit, a counting circuit, and an evaluation circuit. The variable frequency signal source provides a repeating signal having a frequency corresponding to a value of an analog input. The timing circuit defines a timing sequence including a first time interval and a second time interval and generates a mode select signal at a time between the first time interval and the second time interval to stimulate a change in the analog input. The counting circuit is coupled to the timing circuit to count the periods of the repeating signal. The evaluation circuit coupled generates a decision signal in response to a count of the periods of the repeating signal indicated by the counting circuit. The first time interval is not equal to the second time interval to generate an offset in the decision signal.

Claims

1. A time-differential analog comparator, comprising:

a variable frequency signal source coupled to provide a repeating signal having a plurality of periods, wherein each period has a frequency corresponding to a value of an analog input;

a timing circuit coupled to define a timing sequence including a first time interval and a second time interval, wherein the timing circuit begins the timing sequence in response to a begin compare signal and ends the timing sequence in response to a timing complete signal, and wherein the timing circuit generates a mode select signal at a time between the first time interval and the second time interval to stimulate a change in the analog input;

a counting circuit coupled to the timing circuit to count the periods of the repeating signal, wherein the counting circuit is a bidirectional counter coupled to count in a first direction for the first time interval and coupled to count in a second direction opposite to the first direction for the second time interval that starts after an end of the first time interval, wherein the counting circuit generates a count-up signal and a count-down signal and outputs a digital count signal; and

an evaluation circuit coupled to the counting circuit and the timing circuit, wherein the evaluation circuit generates a decision signal in response to a count of the periods of the repeating signal indicated by the digital count signal after an end of the second time interval, wherein the first time interval is not equal to the second time interval to generate an offset in the decision signal.

2. The time-differential analog comparator of claim 1, wherein the analog input is an electrical signal.

3. The time-differential analog comparator of claim 1, wherein the analog input is an intrinsic parameter of a component of a circuit.

4. The time-differential analog comparator of claim 3, wherein the component of the circuit is included in an integrated circuit.

5. The time-differential analog comparator of claim 3, wherein the intrinsic parameter is responsive to temperature.

6. The time-differential analog comparator of claim 1, wherein the timing circuit is responsive to an input that begins the timing sequence.

7. The time-differential analog comparator of claim 6 wherein the timing sequence includes a pause interval between the first time interval and the second time interval.

8. The time-differential analog comparator of claim 1 wherein the timing circuit is coupled to generate the mode select signal to change an external parameter between the first time interval and the second time interval.

9. The time-differential analog comparator of claim 1, wherein at least one signal selected from the group consisting of:

the count-up signal, the count-down signal, and the timing complete signal are provided from an external source.