Data storage in analog memory cells using modified pass voltages

• US 8,498,151 B1
• Filed: 08/04/2009
• Issued: 07/30/2013
• Est. Priority Date: 08/05/2008
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Winter, Shai, Shalvi, Ofir
• Primary Examiner(s): LE, TOAN K
• Application Number:
  US12/534,893
• Time in Patent Office: 1,456 Days
• Field of Search: 365/185.02, 365/185.03, 365/185.09
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

A method for data storage includes storing data in a target analog memory cell, which is one of a group of analog memory cells that are connected in series with one another, by writing a storage value into the target memory cell. The storage value written into the target memory cell is verified while biasing the other memory cells in the group with respective first pass voltages. After writing and verifying the storage value, the storage value is read from the target memory cell while biasing the other memory cells in the group with respective second pass voltages, wherein at least one of the second pass voltages applied to one of the other memory cells in the group is lower than a respective first pass voltage applied to the one of the other memory cells. The data is reconstructed responsively to the read storage value.

Claims

1. A method for data storage, comprising:

storing data in a target analog memory cell, which is one of a group of analog memory cells that are connected in series with one another, by writing a storage value into the target memory cell;

verifying the storage value written into the target memory cell while biasing the other memory cells in the group with respective first pass voltages;

after writing and verifying the storage value, reading the storage value from the target memory cell while biasing the other memory cells in the group with respective second pass voltages, wherein at least one of the second pass voltages applied to one of the other memory cells in the group is lower than a respective first pass voltage applied to the one of the other memory cells; and

reconstructing the data responsively to the read storage value.

2. The method according to claim 1, wherein the analog memory cells comprise NAND Flash memory cells, and wherein the group of the analog memory cells comprises a NAND string.

3. The method according to claim 1, wherein biasing the other memory cells in the group comprises applying the lower at least one of the second pass voltages to a memory cell that neighbors the target memory cell.

4. The method according to claim 1, wherein biasing the other memory cells comprises identifying a subset of the other memory cells in the group, which are unlikely to affect an electrical conductance of the group when biased with the lower at least one of the second pass voltages, and selectively applying the lower at least one of the second pass voltages only to the memory cells in the subset.

5. The method according to claim 4, wherein the memory cells comprise multi-level analog memory cells that are each configured to store a predefined number of bits, and wherein identifying the subset comprises identifying the memory cells in the group that store less than the predefined number of bits.

6. The method according to claim 4, wherein the memory cells comprise multi-level analog memory cells that are each programmed to one of multiple predefined storage value ranges, and wherein identifying the subset comprises identifying the memory cells in the group that are programmed to less than a highest range among the storage value ranges.

7. The method according to claim 1, wherein, at a time of reading the storage value from the target memory cell while biasing the one of the other memory cells with the first pass voltage, the storage value is lower than a minimum readable value, and wherein biasing the one of the other memory cells with the second pass voltage comprises reducing the minimum readable value.

8. The method according to claim 7, wherein the minimum readable value comprises zero while biasing the one of the other memory cells with the first pass voltage.

9. The method according to claim 7, wherein reading the storage value comprises sensing an electrical conductance of the group of the memory cells while applying a non-negative read voltage to the target memory cell.

10. The method according to claim 1, wherein reading the storage value comprises applying a read voltage to the target memory cell, and wherein biasing the other memory cells comprises setting the at least one of the second pass voltages depending on the read voltage.

11. The method according to claim 1, wherein reading the storage value comprises applying a read voltage to the target memory cell, and wherein biasing the other memory cells comprises applying the read voltage to the one of the other memory cells.

12. The method according to claim 1, and comprising applying the lower at least one of the second pass voltages only responsively to a failure to reconstruct the data while biasing the other memory cells in the group with the first pass voltages.

13. The method according to claim 1, wherein the memory cells are comprised in a memory device, and wherein biasing the other memory cells comprises instructing the memory device, using a processor separate from the memory device, to apply the at least one of the second pass voltages.

14. The method according to claim 1, wherein biasing the other memory cells comprises programming a neighboring memory cell in the group to a given storage value, and biasing the neighboring memory cell with a given pass voltage in a vicinity of the given storage value.

15. A method, comprising:

reading an output storage value from a target memory cell in a group of memory cells that are connected in series, wherein the reading includes biasing one of the other memory cells in the group with a pass voltage that is based on a storage value of the other memory cell.

16. The method according to claim 15,

wherein the setting comprises:

determining that the one of the other memory cells is programmed to the storage value and that a second one of the other memory cells is programmed to a second storage value;

setting the pass voltage to a first value based on the determining;

setting a second pass voltage to a second value based on the determining, wherein the second pass voltage biases the second one of the other memory cells;

wherein the first value is lower than the second value, and wherein the storage value is lower than the second storage value.

17. The method according to claim 15, wherein the memory cells comprise multi-level NAND Flash memory cells, and wherein the group of memory cells comprises a NAND string.

18. A method, comprising:

reading an output storage value from a target memory cell in a group of memory cells that are connected in series;

wherein the reading includes;

applying a read threshold to the target memory cell; and

biasing one of the other memory cells in the group with a pass voltage that is based on the read threshold.

19. The method according to claim 18, wherein the memory cells comprise multi-level NAND Flash memory cells, and wherein the group of memory cells is arranged in a NAND string.

20. The method according to claim 18, wherein the other memory cell neighbors the target memory cell.

21. An apparatus, comprising:

an interface, configured to communicate with a memory comprising a group of memory cells that are connected in series; and

circuitry, configured to;

store data in a target analog memory cell in the group by writing a storage value into the target memory cell;

verify the storage value written into the target memory cell while biasing the other memory cells in the group with respective first pass voltages; and

read the storage value from the target memory cell, after writing and verifying the storage value, wherein, to read the storage value, the circuitry is configured to bias the other memory cells in the group with respective second pass voltages;

wherein one of the second pass voltages applied to one of the other memory cells in the group is lower than a respective first pass voltage applied to the one of the other memory cell.

22. The apparatus according to claim 21, wherein the analog memory cells comprise NAND Flash memory cells, and wherein the group of the analog memory cells is arranged as a NAND string.

23. The apparatus according to claim 21, wherein the circuitry is configured to apply the one of the second pass voltages to a memory cell that neighbors the target memory cell.

24. The apparatus according to claim 21, wherein the circuitry is configured to identify a subset of the other memory cells in the group and to selectively apply the one of the second pass voltages to the memory cells in the subset.

25. The apparatus according to claim 24, wherein the memory cells comprise multi-level analog memory cells that are configured to store a predefined number of bits, and wherein the circuitry is configured to identify the subset by identifying memory cells in the group that store less than the predefined number of bits.

26. The apparatus according to claim 24, wherein the memory cells comprise multi-level analog memory cells that are programmed to one of multiple predefined storage value ranges, and wherein the circuitry is configured to identify the subset by identifying memory cells in the group that are programmed to a storage value range that is lower than a highest range among the storage value ranges.

27. The apparatus according to claim 21, wherein the circuitry is configured to reduce a minimum readable value associated with the target cell by biasing the one of the other memory cells with the second pass voltage.

28. The apparatus according to claim 27, wherein the minimum readable value is zero when the one of the other memory cells is biased with the first pass voltage.

29. The apparatus according to claim 27, wherein, to read the storage value, the circuitry is configured to sense an electrical conductance of the group of the memory cells while applying a non-negative read voltage to the target memory cell.

30. The apparatus according to claim 21, wherein the circuitry is configured to read the storage value by applying a read voltage to the target memory cell, and to set the one of the second pass voltages based on the read voltage.

31. The apparatus according to claim 21, wherein the circuitry is configured to read the storage value by applying a read voltage to the target memory cell, and to apply the read voltage to the one of the other memory cells as the one of the second pass voltages.

32. The apparatus according to claim 21, wherein the circuitry is configured to:

reconstruct the data responsively to the read storage value; and

apply the one of the second pass voltages in response to a failure to reconstruct the data while biasing the other memory cells in the group with the first pass voltages.

33. The apparatus according to claim 21, wherein the circuitry comprises:

a read/write unit, comprised in a memory device comprising the memory cells; and

a processor, configured to instruct the R/W unit to apply the one of the second pass voltages, wherein the processor is separate from the memory device.

34. The apparatus according to claim 21, wherein the circuitry is configured to read the storage value from the target memory cell by programming a neighboring memory cell in the group to a given storage value and biasing the neighboring memory cell with a given pass voltage that corresponds to the given storage value.

35. An apparatus, comprising:

an interface configured to communicate with a memory comprising a group of multi-level memory cells connected in series; and

circuitry, which is configured to;

read an output storage value from a target memory cell in the group, wherein, to read the output storage value, the circuitry is configured to bias one of the other memory cells in the group with a pass voltage that is based on a value stored in one of the other memory cells.

36. The apparatus according to claim 35, wherein the circuitry is configured to set the pass voltage to a first value based on determining that the one of the other memory cells is programmed to a first storage value, and to set the pass voltage to a second value that is lower than the first value, based on determining that the one of the other memory cells is programmed to a second storage value that is lower than the first storage value.

37. The apparatus according to claim 35, wherein the memory cells comprise multi-level NAND Flash memory cells, and wherein the group of memory cells is arranged as a NAND string.

38. An apparatus, comprising:

an interface, configured to communicate with a memory comprising a group of memory cells that are connected in series; and

circuitry, configured to;

read an output storage value from a target memory cell in the group using a read voltage;

wherein, to read the output storage value, the circuitry is configured to bias one of the other memory cells in the group with a pass voltage that depends on the read voltage.

39. The apparatus according to claim 38, wherein the memory cells comprise multi-level NAND Flash memory cells, and wherein the group of memory cells is arranged in a NAND string.

40. The apparatus according to claim 38, wherein the one of the other memory cells neighbors the target memory cell.