Method for generating a three-dimensional NAND memory with mono-crystalline channels using sacrificial material

• US 8,501,609 B2
• Filed: 02/02/2012
• Issued: 08/06/2013
• Est. Priority Date: 02/02/2012
• Status: Active Grant

• Current Assignee: Tower Semiconductor Limited
• Original Assignee: Tower Semiconductor Limited
• Inventors: Strum, Avi, Roizin, Yakov
• Primary Examiner(s): Luu, Chuong A
• Assistant Examiner(s): ESKRIDGE, CORY W
• Application Number:
  US13/365,228
• Publication Number:
  US 20130052803A1
• Time in Patent Office: 551 Days
• Field of Search: 438/211, 438/479, 438/591, 438/264, 438/705, 438/738, 438/739, 438/752, 438/753, 438/761, 438/763, 257/E21.18, 257/E27.103, 257/E29.309, 257/E21.09, 257/E21.645, 257/E29.255, 365/185.17, 365/185.05
• US Class Current: 438/591
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels

Abstract

A method for generating three-dimensional (3D) non-volatile memory (NVM) arrays includes forming multiple parallel horizontally-disposed mono-crystalline silicon beams that are spaced apart and arranged in a vertical stack (e.g., such that an elongated horizontal air gap is defined between each adjacent beam in the stack), forming separate charge storage layers on each of the mono-crystalline silicon beams such that each charge storage layer includes a high-quality thermal oxide layer that entirely covers (i.e., is formed on the upper, lower and opposing side surfaces of) each of the mono-crystalline silicon beams, and then forming multiple vertically-disposed poly-crystalline silicon wordline structures next to the stack such that each wordline structure is connected to each of the bitline structures in the stack by way of corresponding portions of the separate charge storage layers. The memory cells are accessed during read/write operations by way of the corresponding wordline and bitline structures.

Claims

1. A method for generating a three-dimensional (3D) non-volatile memory (NVM) array comprising:

forming a plurality of parallel horizontally-disposed mono-crystalline silicon beams that are arranged in a vertical stack such that an associated air gap is defined between each adjacent pair of beams in the stack;

forming a charge storage layer on each of the mono-crystalline silicon beams such that each said charge storage layer includes a oxide layer that entirely covers an associated said beam, and forming a plurality of parallel, spaced-apart vertically-disposed wordline structures next to the stack such that each said wordline structure contacts substantially only a vertical side portion of each of said charge storage layers disposed on said plurality of beams in the stack.

2. The method according to claim 1, wherein forming the plurality of parallel horizontally-disposed mono-crystalline silicon beams comprises:

forming alternating layers of mono-crystalline silicon and a sacrificial material over a substrate;

removing portions of the mono-crystalline silicon and sacrificial material layers such that remaining portions of the layers form the stack including said mono-crystalline silicon beams disposed between sacrificial material structures; and

removing the sacrificial material structures from between each adjacent pair of the mono-crystalline silicon beams such that each said adjacent pair of mono-crystalline silicon beams is separated by said associated air gap.

3. The method according to claim 2, wherein forming alternating layers of mono-crystalline silicon and a sacrificial material over a substrate comprises forming a layer of Silicon-Germanium (SiGe) between each adjacent layer of mono-crystalline silicon.

4. The method according to claim 3, wherein removing portions of the mono-crystalline silicon and sacrificial material layers comprises dry-etching the mono-crystalline silicon and SiGe.

5. The method according to claim 4, wherein removing the sacrificial material structures comprises removing the SiGe from between each adjacent layer of mono-crystalline silicon using a wet etch.

6. The method according to claim 1, wherein forming the charge storage layers on each of the mono-crystalline silicon beams comprises:

performing a sacrificial oxide and surface clean on upper, lower and opposing side surfaces of each of the plurality of beams; and

forming a thermal oxide layer on each of the plurality of beams such that the thermal oxide forms a continuous layer on the upper, lower and opposing side surfaces of each of the plurality of beams.

7. The method according to claim 6, wherein forming the charge storage layers on each of the mono-crystalline silicon beams further comprises forming a charge trapping material layer on said thermal oxide layer.

8. The method according to claim 6,

wherein forming said charge trapping material layer comprises one of depositing nano-dots on said thermal oxide layer, forming a silicon-nitride (SiN) layer on said thermal oxide layer, and forming a layer of high-k based Hf_xAl_yO_z on said thermal oxide layer, and

wherein forming the charge storage layers further comprises forming a second oxide layer on the nitrogen layer.

9. The method according to claim 8, wherein forming the second oxide layer on the charge trapping material layer comprises one of performing direct high temperature pyrogenic oxidation of the charge trapping material layer, depositing at least one of a high temperature oxide or other chemical vapor deposition dielectric, performing a nitride oxidation in an in-situ steam generation (ISSG) system, and (iv) performing an atomic layer deposition (ALD) process.

11. The method according to claim 1,

wherein forming said plurality of vertically-disposed wordline structures comprises:

depositing a conductive material layer over the stack, and

patterning the conductive material layer to form said plurality of wordline structures,

wherein depositing said conductive material layer comprises depositing one of poly-crystalline silicon, a metal, and a metal alloy, and

wherein patterning the conductive material layer comprises removing portions of said conductive material layer disposed over the stack such that adjacent pairs of said wordline structures disposed on opposite sides of said stack are electrically isolated from each other.

12. The method according to claim 1, wherein forming said plurality of vertically-disposed wordline structures further comprises simultaneously forming a select-line structure next to the stack such that said select-line structure contacts a side portion of each of said charge storage layers disposed on said plurality of beams in the stack.

13. The method according to claim 1, wherein forming the plurality of parallel horizontally-disposed mono-crystalline silicon beams comprises forming a plurality of stacks extending between opposing end structures, each stack including a group of said beams, and each adjacent pair of stacks being separated by an intervening trench.

14. The method according to claim 13, wherein forming said plurality of vertically-disposed wordline structures comprises forming a group of said wordline structures in each said intervening trench such that each wordline structure of said group contacts each bitline structure in said adjacent pair of stacks separated by said intervening trench.

15. The method according to claim 13, further comprising forming a protective layer covering the plurality of posts and the plurality of bitline structures.

16. The method according to claim 15, wherein forming said protective layer comprises forming undoped silicate glass (USG) over the plurality of posts and the plurality of bitline structures.

17. The method according to claim 13, further comprising:

patterning service portions of said bitline structures extending into said opposing end structures such that said end structures in each said stack define a staircase arrangement, and

applying an N+ dopant to said service portions of said bitline structures.

18. The method according to claim 17, further comprising forming a plurality of metal contacts, each said metal contact being disposed on an associated service portion of said plurality of bitline structures.

10. A method for generating a three-dimensional (3D) non-volatile memory (NVM) array comprising:

forming a plurality of spaced-apart, parallel, horizontally-disposed mono-crystalline silicon beams that are arranged in a plurality of vertical stacks such that a trench is defined between each adjacent pair of stacks of said mono-crystalline silicon beams;

forming a plurality of charge storage layers, each said charge storage layer being disposed on an associated said mono-crystalline silicon beams such that each said charge storage layer includes a first oxide layer that entirely covers an associated one of the mono-crystalline silicon beams, and

forming a plurality of parallel, spaced-apart vertically-disposed wordline structures next to each stack such that each said wordline structure contacts a corresponding portion of said charge storage layers formed on each of the plurality of beams in at least one associated stack of said plurality of stacks, wherein the corresponding portions are disposed on a vertical side edge of each beam in the at least one associated stack.

20. The method according to claim 10, wherein forming said plurality of vertically-disposed wordline structures comprises:

depositing a single conductive material layer over the plurality of vertical stacks such that the single conductive material layer fills each said trench, and

patterning the conductive material layer to form said plurality of wordline structures such that at least one said wordline structure disposed in a first trench contacts a side portion of each of said charge storage layers disposed on said plurality of beams in both first and second stacks separated by said first trench.

19. A method for generating a three-dimensional (3D) non-volatile memory (NVM) array comprising:

forming a plurality of parallel horizontally-disposed mono-crystalline silicon beams that are spaced apart and arranged in a vertical stack;

forming a charge storage layer on each of the mono-crystalline silicon beams such that horizontal portions of the charge storage layers disposed on opposing surfaces of each adjacent pair of mono-crystalline silicon beams are separated by an air gap; and

forming a plurality of parallel, spaced-apart vertically-disposed wordline structures next to the stack such that each said wordline structure is connected to each of the plurality of mono-crystalline silicon beams in the stack by way of corresponding vertical portions of each said charge storage layer, wherein the corresponding vertical portions are disposed on side edges of the bitline structures and form memory devices.