Semiconductor memory device

• US 8,507,907 B2
• Filed: 01/27/2011
• Issued: 08/13/2013
• Est. Priority Date: 01/29/2010
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takahashi, Yasuyuki, Saito, Toshihiko
• Primary Examiner(s): Landau, Matthew
• Assistant Examiner(s): Chin, Edward
• Application Number:
  US13/015,247
• Publication Number:
  US 20110186837A1
• Time in Patent Office: 929 Days
• Field of Search: 257/43, 257/E29.068, 365/129
• US Class Current: 257/43
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2216/26 Floating gate memory which is adapted to be one-time programmable [OTP], e.g. containing multiple OTP blocks permitting limited update ability
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

It is to provide a semiconductor memory device in which high voltage is not needed in writing, a defect is less likely to occur, the writing time is short, and data cannot be rewritten without an increase in cost. The semiconductor memory device includes a memory element which includes a diode-connected first transistor, a second transistor whose gate is connected to one terminal of a source electrode and a drain electrode of the diode-connected first transistor, and a capacitor connected to the one terminal of the source electrode and the drain electrode of the diode-connected first transistor and the gate of the second transistor.

Claims

1. A semiconductor memory device comprising:

a memory element including a first transistor, a second transistor, and a capacitor; and

a readout circuit;

wherein a gate of the first transistor is electrically connected to one of a source and a drain of the first transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor,

wherein the first transistor includes an oxide semiconductor film,

wherein a first electrode of the capacitor is electrically connected to the gate of the second transistor, and

wherein one of a source and a drain of the second transistor is electrically connected to the readout circuit.

2. The semiconductor memory device according to claim 1, wherein a potential of a second electrode of the capacitor is a fixed potential.

3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a NAND type memory.

4. The semiconductor memory device according to claim 1, wherein carrier density of the oxide semiconductor film is less than 5×

10¹⁴ /cm³.

5. The semiconductor memory device according to claim 1,

wherein the second transistor includes a semiconductor film, and

wherein a material included in the semiconductor film is different from that included in the oxide semiconductor film.

6. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a write-once memory.

7. A semiconductor device including the semiconductor memory device according to claim 1.

8. A semiconductor memory device comprising:

a first wiring;

a second wiring;

a third wiring;

a fourth wiring; and

a memory element including a first transistor, a second transistor, a third transistor, and a capacitor,

wherein a gate of the first transistor is electrically connected to one of a source and a drain of the first transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the second transistor is electrically connected to the first wiring,

wherein one of a source and a drain of the third transistor is electrically connected to the gate of the first transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to the second wiring,

wherein a gate of the third transistor is electrically connected to the third wiring,

wherein a first electrode of the capacitor is electrically connected to the gate of the second transistor,

wherein a second electrode of the capacitor is electrically connected to the fourth wiring, and

wherein the first transistor includes an oxide semiconductor film.

9. The semiconductor memory device according to claim 8, wherein carrier density of the oxide semiconductor film is less than 5×

10¹⁴ /cm³.

10. The semiconductor memory device according to claim 8,

wherein the second transistor includes a semiconductor film, and

wherein a material included in the semiconductor film is different from that included in the oxide semiconductor film.

11. The semiconductor memory device according to claim 8, wherein the semiconductor memory device is a write-once memory.

12. A semiconductor device including the semiconductor memory device according to claim 8.