Electrostatic discharge protection device
First Claim
1. An electrostatic discharge (ESD) protection device, comprising:
- a substrate comprising a first conductive type;
a first doped region formed in the substrate and comprising a second conductive type, wherein the first and the second conductive types are opposite conductive types;
a second doped region formed in the substrate and comprising the second conductive type;
a third doped region formed in the substrate, comprising the first conductive type and located between and separated from the first and the second doped regions;
a gate formed on an area of the substrate between the first and the second doped regions and comprising a first through hole and a second through hole, wherein the first and the second through holes are both formed within a same contiguous layer for the gate; and
a plurality of separated first contacts passing through the first through hole to directly contact with the third doped region,wherein the same contiguous layer comprises a first closed loop and a second closed loop defining the first and second through holes respectively.
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Abstract
An electrostatic discharge (ESD) protection device including a substrate, a first doped region, a second doped region, and a third doped region, a gate and a plurality of contacts is disclosed. The substrate includes a first conductive type. The first doped region is formed in the substrate and includes a second conductive type. The second doped region is formed in the substrate and includes the second conductive type. The third doped region is formed in the substrate, includes the first conductive type and is located between the first and the second doped regions. The gate is formed on the substrate, located between the first and the second doped regions and comprises a first through hole. The contacts pass through the first through hole to contact with the third doped region.
8 Citations
11 Claims
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1. An electrostatic discharge (ESD) protection device, comprising:
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a substrate comprising a first conductive type; a first doped region formed in the substrate and comprising a second conductive type, wherein the first and the second conductive types are opposite conductive types; a second doped region formed in the substrate and comprising the second conductive type; a third doped region formed in the substrate, comprising the first conductive type and located between and separated from the first and the second doped regions; a gate formed on an area of the substrate between the first and the second doped regions and comprising a first through hole and a second through hole, wherein the first and the second through holes are both formed within a same contiguous layer for the gate; and a plurality of separated first contacts passing through the first through hole to directly contact with the third doped region, wherein the same contiguous layer comprises a first closed loop and a second closed loop defining the first and second through holes respectively. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification
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- Resources
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Current AssigneeNational Chiao Tung University (Government of The Republic of China), Vanguard International Semiconductor Corporation
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Original AssigneeNational Chiao Tung University (Government of The Republic of China), Vanguard International Semiconductor Corporation
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InventorsHuang, Yeh-Jen, Jou, Yeh-Ning, Ker, Ming-Dou, Chen, Wen-Yi, Hung, Chia-Wei, Chiou, Hwa-Chyi
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Primary Examiner(s)Hu, Shouxiang
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Application NumberUS13/040,415Publication NumberTime in Patent Office893 DaysField of Search257/355, 257/356, 257/360, 257/362, 257/173, 257/175, 257/401, 257/E27.11, 361/56US Class Current257/173CPC Class CodesH01L 23/62 Protection against overvolt...H01L 27/0262 including a PNP transistor ...H01L 2924/00 Indexing scheme for arrange...H01L 2924/0002 Not covered by any one of g...
