Data holding circuit

• US 8,513,977 B2
• Filed: 01/07/2010
• Issued: 08/20/2013
• Est. Priority Date: 01/22/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Matsuzaki, Takanori
• Primary Examiner(s): Richardson, Jany
• Application Number:
  US12/683,776
• Publication Number:
  US 20100181384A1
• Time in Patent Office: 1,321 Days
• Field of Search: None
• US Class Current: 326/101
• CPC Class Codes: G06K 19/073 Special arrangements for circuits, e.g. for protecting identification code in memory protection against unauthorised use of computer memory G06F12/14
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 17/302 in field-effect transistor switches
• CPC Class Codes: H03K 19/00 Logic circuits, i.e. having at least two inputs acting on one output circuits for computer systems using fuzzy logic G06N7/02; Inverting circuits

Abstract

A semiconductor device which stores data, and in which refresh operation is not needed, is described. The semiconductor device comprises at least a transistor and a capacitor. A first electrode of the capacitor is connected to a reference voltage terminal and a second electrode of the capacitor is connected to one of a source and a drain of the transistor. The semiconductor device is configured to put, when necessary, the other of the source and the drain of the transistor to the same potential as the one of the source and the drain, so that charge accumulated in the capacitor, which is connected to the one of the source and the drain of the transistor, does not leak through the transistor.

Claims

1. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a capacitor; and

a buffer,

wherein one of a source and a drain of the second transistor is electrically connected to an input terminal,

wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the first transistor and one of a source and a drain of the third transistor at a first node,

wherein the other of the source and the drain of the first transistor is electrically connected to one electrode of the capacitor and an input of the buffer at a second node,

wherein the other electrode of the capacitor is electrically connected to a reference voltage terminal,

wherein an output of the buffer is electrically connected to an output terminal and the other of the source and the drain of the third transistor, and

wherein the first node has a lower capacitance than the capacitor.

2. A semiconductor device according to claim 1, wherein the semiconductor device is configured to prevent current leakage through the source and the drain of the first transistor by putting the first transistor and the second transistor in an off state and insuring connection between the output of the buffer and the one of the source and the drain of the first transistor when the first transistor and the second transistor are in the off state.

3. A semiconductor device according to claim 1, wherein the semiconductor device is configured to prevent current leakage of charges accumulated in the capacitor through the source and the drain of the first transistor when the first transistor is in the off state.

4. A semiconductor device comprising:

an antenna;

a rectifier circuit;

a logic portion; and

a flag holding circuit,

wherein the logic portion includes a clock circuit, a logic circuit, a demodulation circuit, and a modulation circuit,

wherein the flag holding circuit includes a first transistor, a second transistor, a third transistor, a capacitor, and a buffer,

wherein the antenna is connected to the rectifier circuit,

wherein the rectifier circuit is connected to the logic portion and the flag holding circuit,

wherein a gate of the second transistor is electrically connected to the logic circuit, one of a source and a drain of the second transistor is electrically connected to an input terminal, and the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the first transistor and one of a source and a drain of the third transistor,

wherein a gate of the first transistor is electrically connected to the logic circuit, and the other of the source and the drain of the first transistor is electrically connected to one electrode of the capacitor and an input of the buffer,

wherein the other electrode of the capacitor is electrically connected to a reference voltage terminal,

wherein an output of the buffer is electrically connected to an output terminal and the other of the source and the drain of the third transistor, and

wherein a gate of the third transistor is electrically connected to the logic circuit.

5. A semiconductor device according to claim 4, wherein the rectifier circuit supplies power supply voltage to the logic portion and the flag holding circuit.

6. A semiconductor device according to claim 4, configured so that,

when the second transistor and the first transistor are turned on, a charge based on a signal received by the antenna is accumulated in the capacitor, and data corresponding to the charge is outputted from the buffer to the output terminal, and

when, after the charge is accumulated, the second transistor and the first transistor are turned off and the third transistor is turned on, and an output from the buffer is applied to one of the source and the drain of the first transistor, the charge is held in the capacitor.

7. A semiconductor device according to claim 6, configured so that,

when the second transistor and the first transistor are turned on, the charge accumulated in the capacitor is released to one of the source and the drain of the first transistor, and data corresponding to a low level of the charge is outputted to the output terminal, and

when, after the charge is released, the second transistor and the first transistor are turned off and the third transistor is turned on, the output from the buffer is applied to one of the source and the drain of the first transistor.

8. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a capacitor; and

a buffer,

wherein one of a source and a drain of the second transistor is electrically connected to an input terminal,

wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the first transistor and one of a source and a drain of the third transistor at a first node,

wherein the other of the source and the drain of the first transistor is electrically connected to one electrode of the capacitor and an input of the buffer at a second node,

wherein the other electrode of the capacitor is electrically connected to a reference voltage terminal,

wherein an output of the buffer is electrically connected to an output terminal and the other of the source and the drain of the third transistor,

wherein the semiconductor device is configured so that

when the second transistor and the first transistor are turned on, a charge originating from the input terminal is accumulated in the capacitor, and data corresponding to the charge is outputted from the buffer to the output terminal, and

when, after the charge is accumulated, the second transistor and the first transistor are turned off and the third transistor is turned on, and an output from the buffer is applied to the one of the source and the drain of the first transistor, the charge is held in the capacitor, and

wherein the first node has a lower capacitance than the second node.

9. A semiconductor device according to claim 8, further comprising:

an antenna;

a rectifier circuit;

a logic portion; and

a flag holding circuit comprising the first transistor, the second transistor, the third transistor, the capacitor and the buffer,

wherein the logic portion includes a clock circuit, a logic circuit, a demodulation circuit, and a modulation circuit,

wherein the antenna is connected to the rectifier circuit,

wherein the rectifier circuit is connected to the logic portion and the flag holding circuit, and

wherein a gate of the first transistor, a gate of the second transistor, and a gate of the third transistor are electrically connected to the logic circuit.

10. A semiconductor device according to claim 8, wherein the semiconductor device is configured to prevent current leakage through the source and the drain of the first transistor by putting the first transistor and the second transistor in an off state and insuring connection between the output of the buffer and the one of the source and the drain of the first transistor when the first transistor and the second transistor are in the off state.

11. A semiconductor device according to claim 8, wherein the semiconductor device is configured to prevent current leakage of charges accumulated in the capacitor through the source and the drain of the first transistor when the first transistor is in the off state.

12. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a capacitor; and

a buffer,

wherein one of a source and a drain of the second transistor is electrically connected to an input terminal,

wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the first transistor and one of a source and a drain of the third transistor at a first node,

wherein the other of the source and the drain of the first transistor is electrically connected to one electrode of the capacitor and an input of the buffer at a second node,

wherein the other electrode of the capacitor is electrically connected to a reference voltage terminal,

wherein an output of the buffer is electrically connected to an output terminal and the other of the source and the drain of the third transistor,

wherein the semiconductor device is configured so that;

when the second transistor and the first transistor are turned on, a charge originating from the input terminal is accumulated in the capacitor, and data corresponding to the charge is outputted from the buffer to the output terminal, and

when, after the charge is accumulated, the second transistor and the first transistor are turned off and the third transistor is turned on, and an output from the buffer is applied to the one of the source and the drain of the first transistor, the charge is held in the capacitor,

when the second transistor and the first transistor are turned on, the charge accumulated in the capacitor is released to one of the source and the drain of the first transistor, and data corresponding to a low level of the charge is outputted to the output terminal, and

when, after the charge is released, the second transistor and the first transistor are turned off and the third transistor is turned on, the output from the buffer is applied to the one of the source and the drain of the first transistor, and

wherein the first node has a lower capacitance than the second node.

13. A semiconductor device according to claim 12, further comprising:

an antenna;

a rectifier circuit;

a logic portion; and

a flag holding circuit comprising the first transistor, the second transistor, the third transistor, the capacitor and the buffer,

wherein the logic portion includes a clock circuit, a logic circuit, a demodulation circuit, and a modulation circuit,

wherein the antenna is connected to the rectifier circuit,

wherein the rectifier circuit is connected to the logic portion and the flag holding circuit, and

wherein a gate of the first transistor, a gate of the second transistor, and a gate of the third transistor are electrically connected to the logic circuit.

14. A semiconductor device according to claim 12, wherein the semiconductor device is configured to prevent current leakage through the source and the drain of the first transistor by putting the first transistor and the second transistor in an off state and insuring connection between the output of the buffer and the one of the source and the drain of the first transistor when the first transistor and the second transistor are in the off state.

15. A semiconductor device according to claim 12, wherein the semiconductor device is configured to prevent current leakage of charges accumulated in the capacitor through the source and the drain of the first transistor when the first transistor is in the off state.