Hardware-based concurrent direct memory access (DMA) engines on serial rapid input/output SRIO interface

• US 8,516,163 B2
• Filed: 02/27/2007
• Issued: 08/20/2013
• Est. Priority Date: 02/27/2007
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Wang, Chi-Lie, Tezcan, Bertan
• Primary Examiner(s): Nam, Hyun
• Application Number:
  US11/679,820
• Publication Number:
  US 20080209084A1
• Time in Patent Office: 2,366 Days
• Field of Search: None
• US Class Current: 710/22
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A serial buffer includes queues configured to store data packets received from a host. A direct memory access (DMA) engine receives data packets from the highest priority queue having a water level that reaches a corresponding watermark. The DMA engine is configured in response to a DMA register set, which is selected from a plurality of DMA register sets. The DMA register set used to configure the DMA engine can be selected in response to information in the header of the read data packet, or in response to the queue from which the data packet is read. Each DMA register set defines a corresponding buffer in system memory, to which the data packet is transferred. Each DMA register set also defines whether the corresponding buffer is accessed in a wrap mode or a stop mode, and whether doorbell signals are generated in response to transfers to the last address in the corresponding buffer.

Claims

1. A serial buffer comprising:

a plurality of queues configured to store data packets received from a host;

a direct memory access (DMA) engine coupled to receive data packets read from the queues;

a plurality of DMA register sets, wherein each of the DMA register sets is configured to store parameters that define a corresponding DMA channel of the DMA engine, and wherein each of the DMA register sets include a start address register configured to store a start address and a stop address register configured to store a stop address, wherein the start address and the stop address define a unique buffer within a system memory, and wherein each of the DMA register sets include a wrap/stop register configured to store a wrap_stop identifier that indicates whether or not the buffer is accessed in a wrap-around manner; and

circuitry for selecting one of the DMA register sets to configure the DMA engine, thereby enabling the DMA engine to transfer the received data packets to the system memory using the corresponding DMA channel.

2. The serial buffer of claim 1, wherein each of the DMA register sets include a next address register configured to load the start address from the start address register.

3. The serial buffer of claim 2, further comprising means for incrementing the next address register of the selected one of the DMA register sets when the DMA engine implements a transfer to the system memory.

4. The serial buffer of claim 3, wherein the DMA engine is configured to access the system memory in response to the contents of the next address register of the selected one of the DMA register sets.

5. The serial buffer of claim 2, further comprising a comparator having inputs coupled to the stop address register and the next address register of the selected one of the DMA register sets.

7. The serial buffer of claim 1, wherein the circuitry for selecting one of the DMA register sets operates in response to which of the queues provides the data packets to the DMA engine.

8. The serial buffer of claim 7, wherein the circuitry for selecting one of the DMA register sets operates in response to information included in the data packets received by the DMA engine.

9. The serial buffer of claim 1, wherein the circuitry for selecting one of the DMA register sets operates in response to information included in the data packets received by the DMA engine.

10. The serial buffer of claim 1, further comprising:

a plurality of water level indicators, each associated with a corresponding one of the queues;

a plurality of watermark indicators, each associated with a corresponding one of the queues; and

a comparator coupled to receive the water level indicators and the watermark indicators, and in response, activate a control signal when a water level indicator associated with a queue reaches a watermark indicator associated with the queue.

11. The serial buffer of claim 10, wherein each of the queues has an assigned priority, further comprising logic for identifying a highest priority queue having an associated water level indicator that has reached the associated watermark indicator.

12. The serial buffer of claim 1, further comprising a plurality of queue channel select registers, each associated with a corresponding one of the queues, and each configured to store a channel select value that defines a DMA register set associated with the corresponding one of the queues.

6. A serial buffer comprising:

a plurality of queues configured to store data packets received from a host;

a direct memory access (DMA) engine coupled to receive data packets read from the queues; and

a plurality of DMA register sets, wherein each of the DMA register sets is configured to store parameters that define a corresponding DMA channel of the DMA engine, and wherein each of the DMA register sets include a start address register configured to store a start address and a stop address register configured to store a stop address, wherein the start address and the stop address define a unique buffer within a system memory, and wherein each of the DMA register sets include a wrap/stop doorbell register configured to store a wrap stop doorbell enable signal that indicates whether or not the serial buffer transmits a doorbell to the host when the DMA engine implements a transfer to an associated stop address; and

circuitry for selecting one of the DMA register sets to configure the DMA engine, thereby enabling the DMA engine to transfer the received data packets to the system memory using the corresponding DMA channel.

13. A serial buffer comprising:

a queue configured to store data packets received from a host, wherein the queue has a queue channel select value and a queue/packet select value;

a direct memory access (DMA) engine coupled to receive data packets read from the queue;

a plurality of DMA register sets, each storing parameters that define a corresponding DMA channel of the DMA engine; and

means for selecting one of the DMA register sets to configure the DMA engine, wherein the means for selecting selects one of the DMA register sets in response to the queue channel select value when the queue/packet select value has a first value, and wherein the means for selecting selects one of the DMA register sets in response to a packet channel select value included in each of the data packets read from the queue when the queue/packet select value has a second value.

14. A serial buffer comprising:

a plurality of queues configured to store data packets received from a host, each of the queues having a corresponding queue channel select value and a corresponding queue/packet select value;

a direct memory access (DMA) engine coupled to receive data packets read from the queues;

a plurality of DMA register sets, each storing parameters that define a corresponding DMA channel of the DMA engine; and

means for selecting one of the DMA register sets to configure the DMA engine, wherein the means for selecting selects one of the DMA register sets in response to the queue channel select value corresponding with a queue being read when the queue/packet select value has a first value, and wherein the means for selecting selects one of the DMA register sets in response to a packet channel select value included in a data packet retrieved from the queue being read when the queue/packet select value has a second value.