Circuit optimization method and apparatus for analog circuit migration

• US 8,516,429 B2
• Filed: 11/15/2011
• Issued: 08/20/2013
• Est. Priority Date: 11/15/2011
• Status: Active Grant

• Current Assignee: Institute of Microelectronics Chinese Academy of Sciences
• Original Assignee: Midtronics Incorporated
• Inventors: Wu, Yuping, Chen, Lan
• Primary Examiner(s): Do, Thuan
• Assistant Examiner(s): Alam, Mohammed
• Application Number:
  US13/640,594
• Publication Number:
  US 20130125080A1
• Time in Patent Office: 644 Days
• Field of Search: 716/113, 716/132
• US Class Current: 716/132
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A circuit optimization apparatus and a circuit optimization method used in analog circuit migration which migrates a source circuit to a target circuit are disclosed. The circuit optimization method comprises: dividing the source circuit into at least one direct current path; determining an adaptation sequence of the at least one direct current path; and optimizing the at least one direct current path in the target circuit one by one in the adaptation sequence. The circuit optimization apparatus and the circuit optimization method improve an optimization efficiency of the analog circuit migration.

Claims

1. A circuit optimization method used in analog circuit migration which migrates a source circuit to a target circuit, comprising:

dividing the source circuit into at least one direct current path by a computer;

determining an adaptation sequence of the at least one direct current path; and

optimizing the at least one direct current path in the target circuit one by one in the adaptation sequence in the source circuit, traversing all devices from voltage supply terminals to ground terminals in a direction of current flow to obtain the at least one direct current path, wherein each of the at least one direct current path comprises all devices that are connected and provide a complete current path between one of the voltage supply terminals and one of the ground terminals; and

in the source circuit, traversing the at least one direct current path from an input terminal to an output terminal in a direction of signal propagation to obtain a signal arrival sequence of the at least one direct current path; and

determining the adaptation sequence of the at least one direct current path; and

setting parameter values of devices in each of the at least one direct current path in the target circuit so that node signals of each of the at least one direct current path in the target circuit meet the design requirement when compared with the corresponding one of the at least direct current path in the source circuit.

2. The circuit optimization method according to claim 1, wherein optimizing the at least one direct current path in the target circuit one by one in the adaptation sequence comprises:

a) selecting one of the at least one direct current path in the target circuit in the adaptation sequence;

b) setting parameter values of the devices in the one of the at least one direct current path in the target circuit;

c) performing target circuit simulation on the one of the at least one direct current path in the target circuit, and on all of the direct current paths which precede the one of the at least one direct current path in the target circuit;

d) analyzing a result of the target circuit simulation to provide node signals of the one of the at least one current path in the target circuit;

e) comparing the node signals of the one of the at least one direct current path in the target circuit with the node signals of the corresponding one of the at least one direct current path in the source circuit; and

f) repeating steps a) to e) under optimization control criteria so that all of the at least one direct current path in the target circuit meet the design requirement.

3. The circuit optimization method according to claim 2, wherein repeating the steps a) to e) under the optimization control criteria comprises:

repeating steps a) to e) while setting new parameter values of the devices to optimize the one of the at least one direct current path in the target circuit, if the one of the at least one direct current path in the target circuit does not meet the design requirement;

repeating steps a) to e) while selecting and optimizing next one of the at least one direct current path in the target circuit, if the one of the at least one direct current path in the target circuit meets the design requirement; and

ending the circuit optimization if all of the at least one direct current path in the target circuit meet the design requirement.

4. The circuit optimization method according to claim 3, wherein repeating steps a) to e) under the optimization control criteria comprises:

repeating steps a) to e) while varying a simulated annealing temperature and/or a genetic generation for new circuit optimization trials, if the number of invalid trials is larger than a maximum in the simulated annealing temperature and/or the genetic generation.

5. The circuit optimization method according to claim 2, wherein setting the parameter values of the devices in the one of the at least one direct current path in the target circuit comprises:

setting initial parameter values of the devices in the one of the at least one direct current path in the target circuit when optimization of the parameter values of the devices starts; and

setting intermediate parameter values of the devices in the one of the at least one direct current path in the target circuit in the optimization of the parameter values of the devices.

6. The circuit optimization method according to claim 5, wherein setting the initial parameter values of the devices in the one of the at least one direct current path in the target circuit comprises:

randomly setting the initial parameter values of the devices in the target circuit;

or

setting the initial parameter values of the devices in the target circuit in accordance with ratios of the devices in the target circuit to the devices in the source circuit and the ratio of a feature size of a new manufacture process to a feature size of a previous manufacture process.

7. The circuit optimization method according to claim 5, wherein setting the intermediate parameter values of the devices in the one of the at least one direct current path in the target circuit comprises:

randomly setting the intermediate parameter values of the devices in the target circuit;

or

varying the intermediate parameter values of the devices in a tendency and an amount that are determined in accordance with difference between an evaluation value of circuit property of the one of the at least one direct current path in the target circuit and a value of circuit property of the corresponding one of the at least one direct current path in the source circuit, and a tendency and an amount of variation of the circuit property by the parameter values of the devices.

8. The circuit optimization method according to claim 7, wherein setting the intermediate parameter values of the devices in the one of the at least one direct current path in the target circuit comprises:

determining optimal parameter values of the devices by linear programming of a plurality of circuit properties.

9. The circuit optimization method according to claim 1, wherein dividing the source circuit into the at least one direct current path comprises:

dividing the source circuit into at least one circuit module; and

subdividing each of the at least one circuit module into at least one direct current path.

10. A circuit optimization apparatus used in analog circuit migration which migrates a source circuit to a target circuit, comprising:

a circuit simulation unit configured to perform source circuit simulation and target circuit simulation;

a circuit simulation result analyzing unit coupled to the circuit simulation unit and configured to calculate node signals of the source circuit and the target circuit in accordance with results of the source circuit simulation and the target circuit simulation;

a circuit connection analyzing unit coupled to the circuit simulation result analyzing unit and configured to analyzing circuit connections of the source circuit to determine direct current paths in the source circuit;

a circuit adaptation sequence determining unit coupled to the circuit connection analyzing unit and configured to analyze a signal arrival sequence of the direct current paths in the source circuit and obtain an adaptation sequence of the direct current paths in the source circuit in accordance with the signal arrival sequence;

a parameter value setting unit coupled to the circuit simulation unit and an optimization control unit, and configured to setting parameter values of the devices in one of the direct current path in the target circuit;

a signal comparison unit coupled to the circuit simulation result analyzing unit, and configured to compare node signals of the one of the direct current paths in the target circuit and the corresponding one of the direct current paths in the source circuit; and

the optimization control unit coupled to the signal comparison unit and the parameter value setting unit, and configured to provide a control signal to the parameter value setting unit in accordance with a comparison result of the signal comparison unit to optimize the direct current paths in the target circuit one by one in the adaptation sequence.

11. The circuit optimization apparatus according to claim 10, wherein the optimization control unit is configured to:

set new parameter values of the devices to optimize one of the direct current paths in the target circuit, if the one of the direct current paths in the target circuit does not meet the design requirement;

select and optimize next one of the direct current paths in the target circuit, if the one of the direct current paths in the target circuit meets the design requirement; and

end the circuit optimization if all of the direct current paths in the target circuit meet the design requirement.

12. The circuit optimization apparatus according to claim 11, wherein the optimization control unit is configured to:

vary a simulated annealing temperature and/or a genetic generation for new circuit optimization trials, if the number of invalid trials is larger than a maximum in the simulated annealing temperature and/or generation.