Storing contexts for thread switching

• US 8,516,496 B2
• Filed: 07/21/2005
• Issued: 08/20/2013
• Est. Priority Date: 07/27/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Cabillic, Gilbert, Chauvel, Gerard
• Primary Examiner(s): Truong, Camquy
• Application Number:
  US11/186,315
• Publication Number:
  US 20060026390A1
• Time in Patent Office: 2,952 Days
• Field of Search: 718/108, 712/200
• US Class Current: 718/108
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 2212/6012 of operating mode, e.g. cache mode or local memory mode
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An electronic device comprising decode logic that decodes instructions and a stack coupled to the decode logic. A group of instructions causes the decode logic to push onto the stack, after halting processing of a first thread at a switch point and prior to processing a second thread, a minimum amount of information needed to resume execution of the first thread at the switch point and not information not needed to resume execution of the first thread at the switch point.

Claims

1. An electronic device, comprising:

a processor configured to execute a first thread and a second thread;

a memory coupled to the processor and configured to store a first stack used by the first thread,

wherein the processor is further configured to switch from execution of the first thread to execution of the second thread by halting the first thread at a switch point; and

executing a minimum context push instruction comprised in a first instruction set of the processor, wherein execution of the minimum context push instruction pushes a minimum context of the first thread onto the first stack, wherein the minimum context comprises at least a program counter and a status register; and

wherein the memory is further configured to store a second stack used by the second thread, and the processor is further configured to switch by executing a minimum context POP instruction comprised in the first instruction set of the processor, wherein execution of the minimum context pop instruction pop a minimum context of the second thread from the second stack.

2. The electronic device of claim 1, wherein the minimum context of the first thread consists of two program counters and a status register of the processor.

3. The electronic device of claim 2, wherein the two program counters are a program counter for the first instruction set of the processor and a program counter for a second instruction set of the processor.

4. The electronic device of claim 1, wherein the processor is further configured to switch by pushing a base address of local variables of the first thread onto the first stack.

5. The electronic device of claim 1, wherein the processor is further configured to switch by storing an address of a topmost stack entry of the first stack in a memory.

6. A processor configured to switch between a first thread and a second thread executable on the processor, the processor comprising:

a memory adapted to store a first stack used by the first thread; and

a decode logic adapted to decode a minimum context push instruction retrieved from the memory at a switch point in the first thread,

wherein the minimum context push instruction is in a first instruction set of the processor, and

wherein execution of the minimum context push instruction causes the processor to push onto the first stack a minimum context of the first thread, wherein the minimum context comprises at least a program counter and a status register, and

wherein the memory is further adapted to store a second stack used by the second thread, and the decode logic is further adapted to decode a minimum context pop instruction retrieved from the memory at the switch point, wherein the minimum context pop instruction is in the first instruction set of the processor, and wherein execution of the minimum context pop instruction causes the processor to pop a minimum context of the second thread from the second stack.

7. The processor of claim 6, wherein the minimum context of the first thread consists of two program counters and a status register of the processor.

8. The processor of claim 7, wherein the two program counters are a program counter for the first instruction set of the processor and a program counter for a second instruction set of the processor.

9. The processor of claim 6, wherein the decode logic is further adapted to store in a different memory an address of a topmost stack entry of the first stack.

10. A method for switching from a first thread executing on a processor to a second thread executing on the processor, the method comprising:

switching from execution of the first thread to execution of the second thread by halting the first thread at a switch point;

executing a minimum context push instruction comprised in a first instruction set of the processor, wherein execution of the minimum context push instruction pushes a minimum context of the first thread onto a first stack used by the first thread, wherein the minimum context comprises at least a program counter and a status register; and

executing a minimum context pop instruction comprised in the first instruction set of the processor, wherein execution of the minimum context pop instruction pop a minimum context of the second thread from a second stack used by the second thread.

11. The method of claim 10, further comprising pushing a base address of local variables of the first thread onto the first stack.

12. The method of claim 10, wherein the minimum context of the first thread consists of two program counters and a status register of the processor.

13. The method of claim 12, wherein the two program counters are a program counter for the first instruction set of the processor and a program counter for a second instruction set of the processor.

14. The method of claim 13, wherein the first instruction set is a stack-based instruction set and the second instruction set is a register-based instruction set.