Image display apparatus and control method therefor

• US 8,519,918 B2
• Filed: 12/22/2010
• Issued: 08/27/2013
• Est. Priority Date: 03/05/2002
• Status: Active Grant

• Current Assignee: Gold Charm Limited (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Gold Charm Limited (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Sasaki, Isao, Iguchi, Koichi
• Primary Examiner(s): Pervan, Michael
• Application Number:
  US12/976,757
• Publication Number:
  US 20110090210A1
• Time in Patent Office: 979 Days
• Field of Search: 345 76- 83
• US Class Current: 345/77
• CPC Class Codes: G09G 2300/0465 Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2310/0254 Control of polarity reversal in general, other than for liquid crystal displays
• CPC Class Codes: G09G 2310/0256 with the purpose of reversing the voltage across a light emitting or modulating element within a pixel
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3241 the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror

Abstract

An image display apparatus comprises a pixel having a drive transistor and a pixel display element which are connected in series between a first power line and a second power line, a holding capacitor connected to a gate electrode of the drive transistor, and a selection transistor connected between a signal line and the gate electrode of the drive transistor. When the selection transistor is turned on, gradation pixel data is written in the holding capacitor from the signal line. The charge of gradation pixel data written in the holding capacitor is discharged for a certain period through the drive transistor, thereafter the charge of the gradation pixel data stored in the holding capacitor is held by floating the gate electrode of the drive transistor.

Claims

1. A drive circuit for a current control element, comprising:

a drive transistor and a current control element which are connected in series between a first power line and a second power line;

a holding capacitor connected to a gate electrode of said drive transistor; and

a selection transistor connected between a signal line and the gate electrode of said drive transistor;

wherein said selection transistor is turned on to apply a first signal voltage to the gate electrode of said drive transistor from said signal line to discharge signal charges written in said holding capacitor through said drive transistor in a selection period of said drive circuit, thereafter a second signal voltage is input from said signal line and held in said holding capacitor, and said selection transistor is turned off to pass a current through said drive transistor to said current control element in a non-selection period of said drive circuit, and

wherein, in an initial stage of the selection period of said drive circuit, said drive transistor is turned on by applying a third signal voltage to the gate electrode of the drive transistor for a duration and a potential of said first power line is brought to a potential of said second power line to discharge charges stored in a parasitic capacitor of said current control element to said first power line via said drive transistor, and then the potential of said first power line is recovered to an original potential of said first power line after a potential of the gate electrode of said drive transistor is transferred from the third signal voltage to the first signal voltage due to expiration of the duration.

2. The drive circuit according to claim 1, wherein said holding capacitor is connected between a junction between said drive transistor and said current control element and the gate electrode of said drive transistor.

3. The drive circuit according to claim 1, wherein a resetting signal voltage is input to said signal line to reset charges stored in said holding capacitor and said parasitic capacitor of said current control element in an initial stage of the selection period of said drive circuit.

4. The drive circuit according to claim 1, wherein said drive transistor is turned on to set said first power line to a resetting signal voltage thereby to reset charges stored in said holding capacitor and said parasitic capacitor of said current control element in an initial stage of the selection period of said drive circuit.

5. The drive circuit according to claim 1, wherein each of said selection transistor and said drive transistor comprises an N-channel field-effect transistor.

6. The drive circuit according to claim 1, wherein each of said selection transistor and said drive transistor comprises a P-channel field-effect transistor.

7. The drive circuit according to claim 1, further comprising:

a switching transistor between the gate and source electrodes of said drive transistor;

wherein said switching transistor is turned on to reset charges stored in said holding capacitor and said parasitic capacitor of said current control element in an initial stage of the selection period or the non-selection period of said drive circuit.

8. The drive circuit according to claim 7, wherein each of said selection transistor, said drive transistor, and said switching transistor comprises an N-channel field-effect transistor.

9. The drive circuit according to claim 7, wherein each of said selection transistor, said drive transistor, and said switching transistor comprises a P-channel field-effect transistor.

10. The drive circuit according to claim 1, further comprising:

a switching transistor between the gate electrode of said drive transistor and said second power line;

wherein said switching transistor is turned on to reset charges stored in said holding capacitor and said parasitic capacitor of said current control element in an initial stage of the selection period or the non-selection period of said drive circuit.

11. The drive circuit according to claim 10, wherein each of said selection transistor, said drive transistor, and said switching transistor comprises an N-channel field-effect transistor.

12. The drive circuit according to claim 10, wherein each of said selection transistor, said drive transistor, and said switching transistor comprises a P-channel field-effect transistor.

13. A drive method for a drive circuit including a drive transistor and a current control element which are connected in series between a first power line and a second power line, a holding capacitor connected to a gate electrode of said drive transistor, and a selection transistor connected between a signal line and the gate electrode of said drive transistor, the drive method comprising the steps of:

turning on said selection transistor to apply a first signal voltage to the gate electrode of said drive transistor from said signal line to discharge signal charges written in said holding capacitor through said drive transistor in a selection period of said drive circuit;

inputting, in the selection period, a second signal voltage from said signal line and holding the second signal voltage in said holding capacitor after application of the first signal voltage, and

turning off said selection transistor to pass a current through said drive transistor to said current control element in a non-selection period of said drive circuit,

wherein, in an initial stage of the selection period of said drive circuit, said drive transistor is turned on by applying a third signal voltage to the gate electrode of the drive transistor for a duration and a potential of said first power line is brought to a potential of said second power line to discharge charges stored in a parasitic capacitor of said current control element to said first power line via said drive transistor, and then the potential of said first power line is recovered to an original potential of said first power line after a potential of the gate electrode of said drive transistor is transferred from the third signal voltage to the first signal voltage due to expiration of the duration.

14. The drive method according to claim 13, wherein said holding capacitor is connected between a junction between said drive transistor and said current control element and the gate electrode of said drive transistor.

15. The drive method according to claim 13, wherein a resetting signal voltage is input to said signal line to reset charges stored in said holding capacitor and said parasitic capacitor of said current control element in an initial stage of the selection period of said drive circuit.

16. The drive method according to claim 13, wherein said drive transistor is turned on to set said first power line to a resetting signal voltage thereby to reset charges stored in said holding capacitor and said parasitic capacitor of said current control element in an initial stage of the selection period of said drive circuit.