Phase change memory cycle timer and method

  • US 8,520,458 B2
  • Filed: 06/22/2012
  • Issued: 08/27/2013
  • Est. Priority Date: 09/08/2010
  • Status: Active Grant
First Claim
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1. A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, said HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a phase change memory (PCM) cycle timer, wherein said HDL design structure comprises:

  • at least one reference phase change element (PCE); and

    a circuit that performs a write operation on the at least one reference PCE and substantially immediately thereafter continuously senses and returns a value of a resistance of the at least one reference PCE.

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