Conditional batch buffer execution

• US 8,522,242 B2
• Filed: 12/31/2007
• Issued: 08/27/2013
• Est. Priority Date: 12/31/2007
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jiang, Hong, Gandhi, Wishwesh
• Primary Examiner(s): Puente, Emerson
• Assistant Examiner(s): Labud, Jonathan R
• Application Number:
  US12/006,243
• Publication Number:
  US 20090172676A1
• Time in Patent Office: 2,066 Days
• Field of Search: None
• US Class Current: 718/101
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system

Abstract

A batch computer or batch processor may implement conditional execution at the command level of the batch processor or higher. Conditional execution may involve execution of one batch buffer depending on the results achieved upon execution by another batch buffer.

Claims

1. A batch processor comprising:

a controller;

a command ring buffer, coupled to the controller, including a plurality of batch buffers, each storing a batch program for execution;

the controller to provide a sequence of execution of the batch programs at or above the batch buffer level;

based on the results of execution of one of the batch programs, change the sequence of batch program execution;

wherein the batch processor is a graphics engine;

wherein at least one of the batch programs indicates what to do upon the occurrence of a condition; and

wherein the sequence of execution of the batch programs is provided in response to a semaphore which signals the result of one of the batch programs executed in one batch buffer to another batch buffer.

2. The batch processor of claim 1 wherein the controller is a direct memory access command streamer.

3. The batch processor of claim 2, the streamer to implement the sequence of execution of the batch programs at the command level of said command streamer.

4. The batch processor of claim 1 including two batch processing engines that communicate using semaphore.

5. The batch processor of claim 1 including a device to overwrite the results of a sequence of executions of the batch programs if the sequence turns out to be incorrect based on a condition that is detected upon execution by one batch program.