SOI device with DTI and STI

• US 8,525,292 B2
• Filed: 04/17/2011
• Issued: 09/03/2013
• Est. Priority Date: 04/17/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Doris, Bruce B., Khakifirooz, Ali, Kulkarni, Pranita
• Primary Examiner(s): BOOTH, RICHARD A
• Application Number:
  US13/088,376
• Publication Number:
  US 20120261792A1
• Time in Patent Office: 870 Days
• Field of Search: 257/510, 257347-354
• US Class Current: 257/510
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

An SOI structure including a semiconductor on insulator (SOI) substrate including a top silicon layer, an intermediate buried oxide (BOX) layer and a bottom substrate; at least two wells in the bottom substrate; a deep trench isolation (DTI) separating the two wells, the DTI having a top portion extending through the BOX layer and top silicon layer and a bottom portion within the bottom substrate wherein the bottom portion has a width that is larger than a width of the top portion; and at least two semiconductor devices in the silicon layer located over one of the wells, the at least two semiconductor devices being separated by a shallow trench isolation within the top silicon layer.

Claims

1. An SOI structure comprising:

a semiconductor on insulator (SOI) substrate including a top semiconductor layer, an intermediate buried oxide (BOX) layer and a bottom substrate;

at least two wells in the bottom substrate;

a deep trench isolation (DTI) separating said two wells, the DTI having a top portion extending through the BOX layer and top semiconductor layer and a bottom portion within the bottom substrate wherein the bottom portion has a width that is larger than a width of the top portion; and

at least two semiconductor devices in the semiconductor layer located over one of the wells, the at least two semiconductor devices being separated by a shallow trench isolation (STI) within the top semiconductor layer.

2. The SOI structure of claim 1 wherein the SOI substrate is an extremely thin SOI substrate.

3. The SOI structure of claim 2 wherein the top semiconductor layer has a thickness of 3 to 15 nanometers.

4. The SOI structure of claim 1 wherein the BOX layer has a thickness of 10 to 140 nanometers.

5. The SOI structure of claim 1 further comprising spacers on a wall of the top silicon layer in the DTI and STI.

6. The SOI structure of claim 1 further comprising spacers on a wall of the top silicon layer and BOX layer in the DTI and STI.

7. The SOI structure of claim 1. wherein one of the wells is an N-type well and one of the wells is a P-type well.