Non-volatile memory having 3D array of read/write elements and read/write circuits and method thereof

• US 8,526,237 B2
• Filed: 06/01/2011
• Issued: 09/03/2013
• Est. Priority Date: 06/08/2010
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Samachisa, George, Fasoli, Luca, Li, Yan, Yan, Tianhong
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US13/151,204
• Publication Number:
  US 20110299340A1
• Time in Patent Office: 825 Days
• Field of Search: 365/185.21, 365/63, 365/185.11
• US Class Current: 365/185.21
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/235 between different crystalline phases, e.g. cubic and hexagonal
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8822 Sulfides, e.g. CuS
• CPC Class Codes: H10N 70/8825 Selenides, e.g. GeSe
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/884 : Other compounds of groups 13-15, e.g. elemental or compound semiconductors
• CPC Class Codes: H10N 70/8845 : Carbon or carbides

Abstract

A three-dimensional array is especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. During sensing, to compensate for word line resistance, a sense amplifier references a stored reference value during sensing of a memory element at a given location of the word line. A layout with a row of sense amplifiers between two memory arrays is provided to facilitate the referencing. A selected memory element is reset without resetting neighboring ones when it is subject to a bias voltage under predetermined conditions.

Claims

1. A memory, comprising:

first and second arrays of non-volatile re-programmable memory elements, wherein a selected row of re-programmable memory elements in each array is accessible by a selected word line and a selected row of bit lines at a plurality of crossing with the selected word line;

a reference row of non-volatile reprogrammable memory elements in each of the first and second arrays for storing a value associated a location of the word line at each crossing so as to provide a reference adjustment to compensate the location due to finite resistance along the word line;

a row of sensing circuits disposed between first and second arrays,

a set of global bit lines traversing said first and second arrays and said row of sensing circuits, each global bit line having in-line first and second segments, the first segment for coupling a respective bit line of a selected row of bit lines in said first array to a respective sensing circuit in said row of sensing circuits, and the second segment for coupling a respective bit line of a selected row of bit lines in said second array to a respective sensing circuit in said row of sensing circuits; and

wherein

when coupled to sense a selected row in said first array, said row of sensing circuits simultaneously are coupled to reference the reference row in the second array; and

when coupled to sense a selected row in said second array, said row of sensing circuits simultaneously are coupled to reference the reference row in said first array.

2. The memory as in claim 1, wherein:

said first and second arrays each comprises;

memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes stacked in the z-direction;

a plurality of local bit lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction; and

wherein;

said first and second segments simultaneously couple a respective sensing circuit of the row of sensing circuits to a respective local bit line in a row of local bit lines in each of said first and second arrays.

3. The memory as in claim 1, wherein:

the row of sensing circuits comprises a corresponding row of comparators;

each comparator having first and second inputs and an output;

the first and second segments respectively simultaneous coupling to the first and second inputs of a respective comparator of the corresponding row of comparators.

4. The memory as in claim 1, wherein:

the word line is being driven by a word line driver from one end; and

the value stored in the reference row at each crossing is a function of a displacement of the crossing from the word line driver.

5. The memory as in claim 1, wherein:

the output of each comparator provides an adjustment for the sensing circuit to compensate for compensating the finite resistance along the selected word line during sensing.

6. A method of sensing a memory, comprising:

providing first and second arrays of non-volatile re-programmable memory elements;

accessing a selected row of re-programmable memory elements in each array by a selected word line and a selected row of bit lines at a plurality of crossing with the selected word line;

storing predetermined values among the memory elements in a designated reference row in each of the first and second arrays so as to provide a reference adjustment to compensate for finite resistance along the word line at each crossing;

providing a row of sensing circuits disposed between first and second arrays,

providing a set of global bit lines traversing said first and second arrays and said row of sensing circuits, each global bit line having in-line first and second segments, the first segment for coupling a respective bit line of a selected row of bit lines in said first array to a respective sensing circuit in said row of sensing circuits, and the second segment for coupling a respective bit line of a selected row of bit lines in said second array to a respective sensing circuit in said row of sensing circuits; and

wherein

when coupled to sense a selected row in said first array, said row of sensing circuits simultaneously are coupled to reference the reference row in the second array; and

when coupled to sense a selected row in said second array, said row of sensing circuits simultaneously are coupled to reference the reference row in said first array.

7. The method as in claim 6, wherein:

said first and second arrays each comprises;

memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes stacked in the z-direction;

a plurality of local bit lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction; and

wherein;

said first and second segments simultaneously couple a respective sensing circuit of the row of sensing circuits to a respective local bit line in a row of local bit lines in each of said first and second arrays.

8. The method as in claim 6, wherein:

the row of sensing circuits comprises a corresponding row of comparators;

each comparator having first and second inputs and an output;

the first and second segments respectively simultaneous coupling to the first and second inputs of a respective comparator of the corresponding row of comparators.

9. The method as in claim 6, wherein, wherein:

the word line is being driven by a word line driver from one end; and

the value stored in the reference row at each crossing is a function of a displacement of the crossing from the word line driver.

10. The method as in claim 6, wherein, wherein:

the output of each comparator provides an adjustment for the sensing circuit to compensate for compensating the finite resistance along the selected word line during sensing.